Patents by Inventor Jean Audet
Jean Audet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11388821Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: GrantFiled: April 17, 2020Date of Patent: July 12, 2022Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 11209598Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.Type: GrantFiled: February 28, 2019Date of Patent: December 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Barnim Alexander Janta-Polczynski, Isabel De Sousa, Jean Audet, Maryse Cournoyer, Sylvain Pharand, Roxan Lemire, Louis-Marie Achard, Paul Francis Fortier
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Patent number: 10949600Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: GrantFiled: August 13, 2019Date of Patent: March 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
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Patent number: 10813215Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: GrantFiled: March 14, 2016Date of Patent: October 20, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, KYOCERA CIRCUIT SOLUTIONS INC.Inventors: Jean Audet, Edmund D. Blackshear, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada
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Patent number: 10806030Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: GrantFiled: January 15, 2015Date of Patent: October 13, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, KYOCERA CIRCUIT SOLUTIONS INC.Inventors: Jean Audet, Edmund D. Blackshear, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada
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Patent number: 10784202Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.Type: GrantFiled: December 1, 2017Date of Patent: September 22, 2020Assignee: International Business Machines CorporationInventors: Francois Arguin, Luc Guerin, Maryse Cournoyer, Steve E. Whitehead, Jean Audet, Richard D. Langlois, Christian Bergeron, Pascale Gagnon, Nathalie Meunier
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Publication number: 20200279840Abstract: A photonic package is provided. The photonic package includes a base substrate defining an aperture, a top die and a photonic integrated circuit (PIC) die. The top die includes a body with first and second top die sections. The first top die section is connectable with the base substrate. The PIC die includes body with first and second PIC die sections. The PIC die is disposable in the aperture such that the second PIC die section is connectable with the second top die section and the first PIC die section extends beyond the second top die section and is exposed for connection to a waveguide assembly.Type: ApplicationFiled: February 28, 2019Publication date: September 3, 2020Inventors: BARNIM ALEXANDER JANTA-POLCZYNSKI, Isabel De Sousa, Jean Audet, Maryse Cournoyer, Sylvain Pharand, Roxan Lemire, Louis-Marie Achard, Paul Francis Fortier
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Publication number: 20200245466Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Inventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10706204Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.Type: GrantFiled: October 2, 2018Date of Patent: July 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Alain Ayotte, Franklin Baez, Anson Call, Deana Cosmadelis, Jason Lee Frankel, Kevin Grosselfinger, Roxan Lemire, Marek Andrzej Orlowski, Gilles Poitras, Paul Robert Walling
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Patent number: 10687420Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.Type: GrantFiled: March 14, 2016Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Edmund D. Blackshear, Masahiro Fukui, Charles L. Reynolds, Kenji Terada, Tomoyuki Yamada
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Patent number: 10660209Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: GrantFiled: November 14, 2017Date of Patent: May 19, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Patent number: 10622299Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.Type: GrantFiled: February 7, 2019Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20200104454Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.Type: ApplicationFiled: October 2, 2018Publication date: April 2, 2020Inventors: Jean Audet, Alain Ayotte, Franklin Baez, Anson Call, Deana Cosmadelis, Jason Lee Frankel, Kevin Grosselfinger, Roxan Lemire, Marek Andrzej Orlowski, Gilles Poitras, Paul Robert Walling
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Publication number: 20190362049Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: ApplicationFiled: August 13, 2019Publication date: November 28, 2019Inventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
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Patent number: 10460956Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.Type: GrantFiled: September 2, 2016Date of Patent: October 29, 2019Assignee: International Business Machines CorporationInventors: Jean Audet, Benjamin V. Fasano, Shidong Li
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Patent number: 10423751Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: GrantFiled: September 29, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling
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Publication number: 20190172787Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Inventors: Francois Arguin, Luc Guerin, Maryse Cournoyer, Steve E. Whitehead, Jean Audet, Richard D. Langlois, Christian Bergeron, Pascale Gagnon, Nathalie Meunier
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Publication number: 20190172784Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.Type: ApplicationFiled: February 7, 2019Publication date: June 6, 2019Inventors: Charles L. Arvin, Jean Audet, Brian W. Quinlan, Charles L. Reynolds, Brian R. Sundlof
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Publication number: 20190150287Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Inventors: Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Jean Audet, Francesco Preda
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Publication number: 20190102505Abstract: Embodiments of the invention include methods, systems, and computer program products for checking floating metals in a laminate structure. Aspects of the invention include receiving, by a processor, floating metal rules and a semiconductor package design having a plurality of laminate layers. Each laminate layer includes a plurality of metal shapes, a plurality of signal lines, and a plurality of vias. The metal shapes, signal lines, and vias are mapped to one or more cells in an array. The processor determines, for each cell corresponding to a metal shape, whether the plurality of vias satisfies the floating metal rules. The processor can suggest new vias to satisfy the floating metal rules.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Jean Audet, Franklin M. Baez, Jason L. Frankel, Paul R. Walling