Patents by Inventor Jean Audet

Jean Audet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7017128
    Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: March 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
  • Publication number: 20050109535
    Abstract: A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.
    Type: Application
    Filed: November 25, 2003
    Publication date: May 26, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jean Audet, Irving Memis
  • Publication number: 20050013124
    Abstract: An area-array integrated circuit package assembly are provided with a plurality of electrically conductive connectors attached to the package I.O. pads, that are used to connect the package to a printed circuit card or other component. The connectors comprise at least two parallel conductors flexing together in the same direction, electrically insulated from each other for a portion of their length between the package and printed circuit card to provide for reduced interconnection inductance. The connection with the component contact pads can be achieved by mechanically pressing the package and circuit card together or with the use of bonding material.
    Type: Application
    Filed: July 30, 2003
    Publication date: January 20, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Luc Guerin, Jean-Luc Landreville, Gerald Audet
  • Publication number: 20040168403
    Abstract: The invention provides a device for use in the extraction of bottles or the like from cartons travelling in a stream on a conveyor, each carton having a bottom wall and associated side walls. The device has a saw blade adapted to extend across the conveyor to cut the associated side walls just above the base which is thereby severed. The saw blade is vertically adjustable so as to accommodate cartons having bases of different thickness' and thereby ensure avoidance of damage to the bottles sitting on said bottom wall. A sensor positioned upstream of said blade determines the vertical position required for each passing carton and transmits a signal which results in the blade being positioned as required.
    Type: Application
    Filed: January 12, 2004
    Publication date: September 2, 2004
    Inventors: Jean Audet, Jean-Guy Comeau
  • Patent number: 6762367
    Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet
  • Publication number: 20040132229
    Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 8, 2004
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
  • Publication number: 20040050585
    Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.
    Type: Application
    Filed: September 17, 2002
    Publication date: March 18, 2004
    Applicant: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet
  • Patent number: 6703706
    Abstract: An electrical structure to optimize a signal wire structure. The electrical structure provides concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
  • Publication number: 20030127728
    Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Application
    Filed: January 8, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
  • Patent number: 6461443
    Abstract: The present invention provides new and improved methods and apparatus for removing contamination from surfaces of substrates. Existing techniques include plasma ashing, glow discharge or UV/ozone processes. The present invention includes cleaning the substrate surfaces by transporting the substrates to be cleaned through a first zone where the substrates are heated preferably in a nitrogen atmosphere and then to a second zone where the substrates are surrounded by an atmosphere of ozone. The organic contamination is thereby vaporized into vapor products including CO, CO2 and H2O.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: October 8, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Mario Leboeuf, Isabelle Tremblay, Herbert P. R. Wossidlo