Abstract: An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.

Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.

Abstract: The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.

Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.

Abstract: An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.

Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.

Abstract: A method and system allow a mobile device user to automatically execute a service application to provide a requested service. The user may enter a USSD code or initiate a voice call to a special number. The wireless network recognizes the user's act as a request for a specific service and notifies the service provider. The service provider sends an activation command to the mobile device and may also initiate installing the service application.

Abstract: The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.

Abstract: A method and system allow a mobile device user to automatically execute a service application to provide a requested service. The user may enter a USSD code or initiate a voice call to a special number. The wireless network recognizes the user's act as a request for a specific service and notifies the service provider. The service provider sends an activation command to the mobile device and may also initiate installing the service application.