Abstract: A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n?1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n?1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that includes a first main line having a first width and a first subline having a second width, and a second line pattern that includes a second main line having the first width and a second subline having a third width. The first line pattern may include a first width changer whose width increases from the first width to the second width. The second line pattern may include a second width changer whose width increases from the first width to the third width.

Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.

Abstract: A display device in a display panel; a backlight unit configured to provide light to the display panel, the display pan& being arranged at a side of a first surface of the backlight unit; and a first light adjustment unit configured to be arranged at a side of a second surface of the backlight unit opposite to the first surface of the backlight unit, the first light adjustment unit including a plurality of reflection portions, reflection portions of the plurality of reflection portions being rotatable so as to be switchable between a light transmission mode and a light reflection mode.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that includes a first main line having a first width and a first subline having a second width, and a second line pattern that includes a second main line having the first width and a second subline having a third width. The first line pattern may include a first width changer whose width increases from the first width to the second width. The second line pattern may include a second width changer whose width increases from the first width to the third width.

Abstract: A secondary battery is disclosed. In one aspect, the battery includes an electrode assembly including i) a positive electrode plate on which a positive active material is formed, ii) a negative electrode plate on which a negative active material is formed, and iii) a separator separating the positive and negative electrode plates. The battery also includes a can accommodating the electrode assembly, wherein the can has an inner surface facing the electrode assembly, an inner active material layer formed on the inner surface of the can and a securing layer covering the inner active material layer.

Abstract: A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.

Abstract: A method of fabricating a flash memory device includes sequentially forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes an upper sacrificial pad portion and an upper sacrificial line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as an etch mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. Finally, a lower mask pattern including at least one line mask, at least one bridge mask, and at least one pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

Abstract: A secondary battery and a method of manufacturing the same are disclosed. In one aspect, the method includes preparing an electrode assembly comprising a positive electrode plate, a negative electrode plate, and a separator interposed therebetween. The method also includes freezing the electrode assembly after the electrode assembly is filled with an electrolyte solution, dipping the frozen electrode assembly in a liquid polymer material, retrieving the dipped electrode assembly from the liquid polymer material, and curing an external surface of the electrode assembly.

Abstract: A display device in a display panel; a backlight unit configured to provide light to the display panel, the display pan& being arranged at a side of a first surface of the backlight unit; and a first light adjustment unit configured to be arranged at a side of a second surface of the backlight unit opposite to the first surface of the backlight unit, the first light adjustment unit including a plurality of reflection portions, reflection portions of the plurality of reflection portions being rotatable so as to be switchable between a light transmission mode and a light reflection mode.

Abstract: A display apparatus includes a display portion configured to display an image, a frame surrounding the display portion, and a block in which a groove is defined. The frame includes a plurality of protrusions. The protrusions have same shapes and are arranged spaced apart by a uniform gap. The groove of the block is configured to receive a protrusion of the frame.

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract: A secondary battery includes an electrolyte; an electrode assembly including: a first electrode plate including a first active material on a first base material, a second electrode plate opposite to the first electrode plate and including a second active material on a second base material, and a separator between the first and second electrode plates; a battery case accommodating the electrode assembly and the electrolyte; and a bridge member coupled between terminal portions having different polarities at the outside of the battery case, wherein the voltage of the secondary battery is ?0.1V to 0.1V.

Abstract: A method of manufacturing a secondary battery is disclosed. In one aspect, a method of manufacturing a secondary battery includes assembling the secondary battery by receiving an electrode assembly including a first pole plate, a second pole plate and a separator between the first and second pole plates, along with an electrolyte, in a battery case. The method further includes precharging the secondary battery, leaving the secondary battery at room temperature and performing first charging and first discharging of the secondary battery.

Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

Abstract: A secondary battery is disclosed. In one aspect, the battery includes an electrode assembly including i) a positive electrode plate on which a positive active material is formed, ii) a negative electrode plate on which a negative active material is formed, and iii) a separator separating the positive and negative electrode plates. The battery also includes a can accommodating the electrode assembly, wherein the can has an inner surface facing the electrode assembly, an inner active material layer formed on the inner surface of the can and a securing layer covering the inner active material layer.

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.