Abstract: A semiconductor device is disclosed, which comprises a capacitor structure formed over a device region of a substrate, and a buffer layer. The capacitor structure comprises a lower electrode having a U-shaped profile that opens away from the substrate, the U-shaped profile defines an interior surface and an opposing exterior surface; a dielectric liner extending into the U-shaped profile and conformally covering the interior surface of the lower electrode; and an upper electrode formed over the dielectric liner, extending into and filling the U-shaped profile, the upper electrode) includes a top conductive layer. The buffer layer formed on the top conductive layer of the upper electrode, wherein the lattice constant of the buffer layer is greater than that of the top conductive layer.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A method for inducing an activity of a user's autonomic nervous system is provided. The method includes steps of: (a) on condition that each of the user's reference heart rate information corresponding to each of active states of the user's autonomic nervous system is obtained, an inducing device, if a specific active state of the autonomic nervous system is selected by the user, acquiring first reference heart rate information of the user corresponding to the specific active state of the autonomic nervous system; and (b) the inducing device supporting a first vibration stimulus with a first period corresponding to the first reference heart rate information to be applied to the user, to thereby allow the user's real-time average cardiac interval to be synchronized with the first vibration stimulus.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: An exemplary embodiment of the present disclosure provides a transistor including: a drain electrode; a first insulating member on the drain electrode and having a tilted side wall; a source electrode on the first insulating member; an active member covering the tilted side wall of the first insulating member, a side wall of the source electrode, and a side wall of the drain electrode; a second insulating member covering the source electrode and the active member; and a gate electrode on the second insulating member and overlapping the active member, wherein the active member defines a first channel region adjacent to the drain electrode and a second channel region adjacent to the source electrode, and wherein a width of the first channel region may be greater than that of the second channel region.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: A touch panel including a substrate a first signal line positioned on the substrate and extending in a first direction while being bent in a second direction several times and a second signal line positioned on the substrate and extending in the second direction while being bent in the first direction intersecting the first direction several times to intersect the first signal line.

Abstract: An exemplary embodiment of the present disclosure provides a transistor including: a drain electrode; a first insulating member on the drain electrode and having a tilted side wall; a source electrode on the first insulating member; an active member covering the tilted side wall of the first insulating member, a side wall of the source electrode, and a side wall of the drain electrode; a second insulating member covering the source electrode and the active member; and a gate electrode on the second insulating member and overlapping the active member, wherein the active member defines a first channel region adjacent to the drain electrode and a second channel region adjacent to the source electrode, and wherein a width of the first channel region may be greater than that of the second channel region.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: A bioelectrode including a plate, a first electrode disposed on a first side of the plate, and a second electrode disposed on the first side of the plate and separate from the first electrode. The bioelectrode further includes a first guard portion disposed on a second side of the plate, a second guard portion disposed on the second side of the plate and separate from the first guard portion, and a preamplifier configured to output a voltage signal based on a biosignal measured between the first electrode and the second electrode.

Abstract: An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.

Abstract: An organic light emitting diode (OLED) display is disclosed. The OLED display includes a substrate, a scan line on the substrate and configured to transfer a scan signal, a data line crossing the scan line and configured to transfer a data signal, a driving voltage line crossing the scan line or the data line and configured to transfer a driving voltage, a switching thin film transistor (TFT) connected to the scan line and the data line, a driving TFT connected to the switching TFT and the driving voltage line, an OLED connected to the driving TFT, and a storage capacitor connected to the driving voltage line and a driving gate electrode of the driving TFT. The storage capacitor includes a first storage capacitor plate that overlaps the driving voltage line.

Abstract: An organic light emitting diode display apparatus and a method and apparatus for easily inspecting the organic light emitting diode display apparatus to determine whether an electrical failure occurs. The organic light emitting diode display apparatus comprises a plurality of pixels each comprising a pixel electrode, an intermediate layer including an organic emission layer, and an opposite electrode; scan lines and data lines corresponding to the plurality of pixels; first power supply lines connected to the plurality of pixels and extending in a first direction; second power supply lines connected to the first power supply lines; and a control line unit for simultaneously supplying control signals to the plurality of pixels, the control line unit including a plurality of control lines extending in one direction and two common lines being respectively connected to both ends of each of the plurality of control lines.

Abstract: A rigid flexible printed circuit board, having a rigid region and a flexible region, includes, in one embodiment: a base substrate including a portion in the rigid region and a portion in the flexible region; a coverlay formed on the base substrate; a first insulating layer formed on the coverlay and formed in the rigid region; a second insulating layer formed on the first insulating layer; and an outer layer circuit layer formed on the second insulating layer. Also described is a method of manufacturing a rigid flexible printed circuit board having a rigid region and a flexible region.

Abstract: A touch panel including a substrate a first signal line positioned on the substrate and extending in a first direction while being bent in a second direction several times and a second signal line positioned on the substrate and extending in the second direction while being bent in the first direction intersecting the first direction several times to intersect the first signal line.

Abstract: A method of inspecting a short circuit defect between first wires extending in a first direction and a second direction intersecting the first direction and second wires extending in the first or second direction, the method including inspecting a short circuit defect between the first and second wires by using a potential difference monitored only in the second wires.

Abstract: A vehicle speed enforcement method includes the steps of receiving and collecting, by a base station located in a detection zone, information about a target vehicle from a communication unit in the target vehicle, detecting a speed of the target vehicle through the collected information about the target vehicle, and setting the target vehicle as an overspeed vehicle when the speed of the target vehicle is faster than a reference limit speed at a point in time at which the target vehicle has entered the detection zone.