Abstract: A method of Ethernet virtualization using hardware control flow override. The method comprises providing, at a first logical entity of a first programmable logic device, control signals used for performing control-flow, selectively routing the control signals to a second programmable logic device that is external to the first programmable logic device, receiving processed control signals from the second programmable logic device, and forwarding the processed control signals to a second logic entity of the first programmable logic device.

Abstract: A packet that represents unknown traffic for a virtual host is received. A first test is performed to ascertain whether or not a destination connection can be determined for the received packet wherein, if a destination connection can be determined, a second test is performed to ascertain whether or not one or more connection-specific resources required to send the packet to a virtual host memory corresponding to the destination connection are available. If a destination connection for the packet cannot be determined, the packet is passed to a store engine. If the one or more connection-specific resources are not available, the packet is passed to the store engine. The store engine obtains a free packet buffer from a FIFO memory. The store engine moves the packet into the free packet buffer and submits the free packet buffer to the elastic FIFO memory.

Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.

Abstract: An incoming LAN traffic management system comprising: an I/O adapter configured to receive incoming packets from an Ethernet; a plurality of hosts coupled to the I/O adapter and each having a host buffer; a data router configured to block information received by the I/O adapter into memory locations from an SBAL associated with at least one of the plurality of hosts and in accordance with blocking parameters for the at least one of the plurality of hosts, the data router including an expiration engine configured to expire the SBAL before it is full if at least one predetermined threshold is exceeded.

Abstract: A packet that represents unknown traffic for a virtual host is received. A test is performed to ascertain whether or not a destination connection can be determined for the received packet wherein it is discovered the packet is a broadcast (or multicast) packet. Since such packets have multiple destinations in a virtualized environment, the broadcast (or multicast) packet requires special handling and is passed to a store engine. The store engine obtains a free packet buffer from an elastic FIFO memory, moves the packet into the free packet buffer, and submits the free packet buffer back to the elastic FIFO memory. An assist engine determines and assigns connections to packets submitted to the elastic FIFO without known connections, such as broadcast (or multicast) packets. The assist engine efficiently performs this task through the use of indirect buffers, which are also obtained from and submitted back to the elastic FIFO.

Abstract: A processor node of a network is provided which includes one or more processors and a virtualized channel adapter. The virtualized channel adapter is operable to reference a table to determine whether a destination of the communication is supported by the virtualized channel adapter. When the destination is supported for routing via hardware, the virtualized channel adapter is operable to route the communication via hardware to at least one of a physical port and a logical port of the virtualized channel adapter. Otherwise, when the destination is not supported for routing via hardware, the virtualized channel adapter is operable to route the communication via firmware to a virtual port of the virtualized channel adapter. A corresponding method and a recording medium having information recorded thereon for performing such method are also provided herein.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.

Abstract: A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.

Abstract: A method and an apparatus for providing concurrent patch in a computing network environment using microcode and having a queued direct I/O and a main memory in processing communication with an adapter. First it is allowed for a new level of microcode to be installed to an adapter without interrupting any running applications and/or services. It is then determined if the affected adapter is a network or a channel adapter. If the adapter is a channel adapter, applications using the channel adapter are to run without requiring any connection type information to be kept across any code updates. If the adapter is determined to be a network adapter, all adapter sessions are kept alive and activated while accessing information about any client station connected to a LAN and each present in said environment.