Patents by Inventor Jeffrey R. LaRoche
Jeffrey R. LaRoche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848662Abstract: Embodiments of a single-chip ScAIN tunable filter bank include a plurality of switching elements, and a plurality of channel filters integrated on a monolithic platform. The monolithic platform may comprise a single crystal base and each of the switching elements may comprise at least one of a scandium aluminum nitride (ScAIN) or other Group III-Nitride transistor structure fabricated on the single crystal base. In these embodiments, each channel filter comprises a multi-layered ScAIN structure comprising one or more a single-crystal epitaxial ScAIN layers fabricated on the single crystal base. The ScAIN layers for each channel filter may be based on desired frequency characteristics of an associated one of the RF channels.Type: GrantFiled: September 11, 2020Date of Patent: December 19, 2023Assignee: Raytheon CompanyInventors: Jason C. Soric, Jeffrey R. Laroche, Eduardo M. Chumbes, Adam E. Peczalski
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Patent number: 11784248Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.Type: GrantFiled: October 25, 2022Date of Patent: October 10, 2023Assignee: Raytheon CompanyInventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Eduardo M. Chumbes
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Patent number: 11710708Abstract: An integrated circuit structure including a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure; an EMF shield enclosing the substrate, the gallium nitride layer and the photoconductive semiconductor switch laterally disposed alongside the transistor on the gallium nitride layer integrated into the integrated circuit structure; and a signal line electronically coupled with the photoconductive semiconductor switch, the signal line penetrating the EMF shield.Type: GrantFiled: August 19, 2021Date of Patent: July 25, 2023Assignee: RAYTHEON COMPANYInventors: Matthew DeJarld, Jeffrey R. LaRoche, Susan C. Trulli
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Publication number: 20230216480Abstract: A method for fabricating a multi-layer resonator assembly includes sequentially fabricating a plurality of vertically-stacked resonator layers including, for each resonator layer of the plurality of resonator layers, depositing a dielectric layer, forming at least one film bulk acoustic resonator (FBAR) cavity in the deposited dielectric layer, filling each FBAR cavity of the at least one FBAR cavity with a sacrificial material block, and depositing a FBAR material stack over the at least one FBAR cavity. The deposited FBAR material stack is in contact with the sacrificial material block and the dielectric layer. The method further includes removing the sacrificial material block from the at least one FBAR cavity for each resonator layer of the plurality of resonator layers subsequent to sequentially fabricating the plurality of resonator layers.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Inventors: Lovelace Soirez, Jeffrey R. LaRoche
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Publication number: 20230073459Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.Type: ApplicationFiled: October 25, 2022Publication date: March 9, 2023Applicant: Raytheon CompanyInventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Eduardo M. Chumbes
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Publication number: 20230065622Abstract: An Array Core Block for an AESA includes a stack of 2*M alternating N-channel RFIC and MMIC Power Amplifier wafers bonded together by a wafer-scale direct bond hybrid (DBH) interconnect process. This process forms both metal-to-metal and dielectric hydrogen bonds between bonding surfaces to seal the wafer stack. Each array core block includes an array of through substrate metal vias to distribute DC bias, LO and information signals. Each array core block also includes a cooling system including micro-channels formed on a backside of at least one of the chips in each bonded pair and through substrate via holes formed through the stack that operatively couple the micro-channels for all of the bonded pairs to receive and circulate a fluid through the micro-channels and through substrate via holes to cool the RFIC and MMIC Power Amplifier chips and to extract the heated fluid.Type: ApplicationFiled: September 2, 2021Publication date: March 2, 2023Inventors: Miroslav Micovic, Karen Kaneko Baker, Christopher Carbonneau, Katherine J. Herrick, Teresa J. Clement, Jeffrey R. Laroche
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Publication number: 20230056601Abstract: An integrated circuit structure including a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure; an EMF shield enclosing the substrate, the gallium nitride layer and the photoconductive semiconductor switch laterally disposed alongside the transistor on the gallium nitride layer integrated into the integrated circuit structure; and a signal line electronically coupled with the photoconductive semiconductor switch, the signal line penetrating the EMF shield.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Applicant: Raytheon CompanyInventors: Matthew DeJarld, Jeffrey R. LaRoche, Susan C. Trulli
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Patent number: 11581448Abstract: An integrated circuit structure comprising a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure wherein a regrown gallium nitride material is disposed on the photoconductive semiconductor switch and operatively coupled with the wafer.Type: GrantFiled: April 1, 2021Date of Patent: February 14, 2023Assignee: Raytheon CompanyInventors: Matthew DeJarld, Jeffrey R. LaRoche, Clay T. Long, Lovelace Soirez
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Patent number: 11515410Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.Type: GrantFiled: October 30, 2020Date of Patent: November 29, 2022Assignee: Raytheon CompanyInventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Eduardo M. Chumbes
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Patent number: 11476154Abstract: A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.Type: GrantFiled: September 26, 2019Date of Patent: October 18, 2022Assignee: Raytheon CompanyInventors: Jeffrey R. LaRoche, John P. Bettencourt, Paul J. Duval, Kelly P. Ip
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Publication number: 20220320360Abstract: An integrated circuit structure comprising a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure wherein a regrown gallium nitride material is disposed on the photoconductive semiconductor switch and operatively coupled with the wafer.Type: ApplicationFiled: April 1, 2021Publication date: October 6, 2022Applicant: Raytheon CompanyInventors: Matthew DeJarld, Jeffrey R. LaRoche, Clay T. Long, Lovelace Soirez
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Publication number: 20220320152Abstract: An integrated circuit structure comprising a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure.Type: ApplicationFiled: April 1, 2021Publication date: October 6, 2022Applicant: Raytheon CompanyInventors: Matthew DeJarld, Jeffrey R. LaRoche, Clay T. Long, Lovelace Soirez
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Publication number: 20220140126Abstract: A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Applicant: Raytheon CompanyInventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Eduardo M. Chumbes
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Publication number: 20220128409Abstract: Disclosed herein are Raman spectrographic systems and methods of assembling Raman spectrographic systems. The Raman spectrographic system includes a light source to emit ultraviolet incident light into a waveguide, and an interaction region traversed by the waveguide and that holds a sample to be identified. A spectrometer detects Raman scatter from an output light in the waveguide emerging from the interaction region following interaction between the incident light and the sample and output a spectral response. The spectrometer includes an array of detectors. Each detector of the array of detectors is a silicon carbide (SiC) detector to obtain information that includes an intensity corresponding with a wavelength of the Raman scatter. A controller identifies the sample based on the spectral response from the array of detectors.Type: ApplicationFiled: October 27, 2020Publication date: April 28, 2022Inventors: Richard Moro, JR., Erik D. Johnson, Bernard Harris, Jeffrey R. Laroche
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Publication number: 20220085795Abstract: Embodiments of a single-chip ScAIN tunable filter bank include a plurality of switching elements, and a plurality of channel filters integrated on a monolithic platform. The monolithic platform may comprise a single crystal base and each of the switching elements may comprise at least one of a scandium aluminum nitride (ScAIN) or other Group III-Nitride transistor structure fabricated on the single crystal base. In these embodiments, each channel filter comprises a multi-layered ScAIN structure comprising one or more a single-crystal epitaxial ScAIN layers fabricated on the single crystal base. The ScAIN layers for each channel filter may be based on desired frequency characteristics of an associated one of the RF channels.Type: ApplicationFiled: September 11, 2020Publication date: March 17, 2022Inventors: Jason C. Soric, Jeffrey R. Laroche, Eduardo M. Chumbes, Adam E. Peczalski
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Patent number: 11239326Abstract: A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.Type: GrantFiled: April 11, 2019Date of Patent: February 1, 2022Assignee: RAYTHEON COMPANYInventors: Jeffrey R. LaRoche, Kelly P. Ip, Thomas E. Kazior, Kamal Tabatabaie Alavi
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Patent number: 11205953Abstract: A power converter assembly is provided and includes high quality factor (Q) shield-to-transistor integrated low-inductance capacitor elements to divert common mode (CM) currents, high Q shield-to-shield integrated low-inductance capacitor elements to compliment line-to-line filter capacitors and high Q baseplate integrated low-inductance capacitor elements to attenuate residual CM currents.Type: GrantFiled: January 13, 2020Date of Patent: December 21, 2021Assignee: RAYTHEON COMPANYInventors: Boris S. Jacobson, Steven D. Bernstein, Steven M. Lardizabal, Jason Adams, Jeffrey R. Laroche
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Patent number: 11177216Abstract: A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.Type: GrantFiled: September 6, 2018Date of Patent: November 16, 2021Assignee: Raytheon CompanyInventors: Jeffrey R. LaRoche, Eduardo M. Chumbes, Kelly P. Ip, Thomas E. Kazior
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Publication number: 20210273558Abstract: A power converter assembly is provided and includes high quality factor (Q) shield-to-transistor integrated low-inductance capacitor elements to divert common mode (CM) currents, high Q shield-to-shield integrated low-inductance capacitor elements to compliment line-to-line filter capacitors and high Q baseplate integrated low-inductance capacitor elements to attenuate residual CM currents.Type: ApplicationFiled: January 13, 2020Publication date: September 2, 2021Inventors: Boris S. Jacobson, Steven D. Bernstein, Steven M. Lardizabal, Jason Adams, Jeffrey R. Laroche
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Publication number: 20210098285Abstract: A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Applicant: Raytheon CompanyInventors: Jeffrey R. LaRoche, John P. Bettencourt, Paul J. Duval, Kelly P. Ip