Abstract: A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.

Abstract: A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process.

Abstract: A power converter assembly is provided and includes high quality factor (Q) shield-to-transistor integrated low-inductance capacitor elements to divert common mode (CM) currents, high Q shield-to-shield integrated low-inductance capacitor elements to compliment line-to-line filter capacitors and high Q baseplate integrated low-inductance capacitor elements to attenuate residual CM currents.

Abstract: A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process.

Abstract: A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.

Abstract: A modular high-power converter system includes an electronic power distribution unit configured to output an analog current (AC) voltage to a power bus, and at least one Transmit or Receive Integrated Microwave Module (T/RIMM) that includes a voltage converter unit and a transmitter and receiver (T/R) unit. The voltage converter unit includes at least one analog-to-digital converter (ADC) to convert the AC voltage into a direct current (DC) voltage having a first DC voltage level. The transmitter and receiver (T/R) unit includes a modular-based DC/DC converter to convert the DC voltage into a second DC voltage having a second voltage. The modular-based DC/DC converter includes a modular power converter unit configured to generate the second DC voltage. The modular converter unit is configured to be independently interchangeable with a different modular converter unit.

Abstract: A power converter assembly is provided and includes high quality factor (Q) shield-to-transistor integrated low-inductance capacitor elements to divert common mode (CM) currents, high Q shield-to-shield integrated low-inductance capacitor elements to compliment line-to-line filter capacitors and high Q baseplate integrated low-inductance capacitor elements to attenuate residual CM currents.

Abstract: A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.

Abstract: A modular high-power converter system includes an electronic power distribution unit configured to output an analog current (AC) voltage to a power bus, and at least one Transmit or Receive Integrated Microwave Module (T/RIMM) that includes a voltage converter unit and a transmitter and receiver (T/R) unit. The voltage converter unit includes at least one analog-to-digital converter (ADC) to convert the AC voltage into a direct current (DC) voltage having a first DC voltage level. The transmitter and receiver (T/R) unit includes a modular-based DC/DC converter to convert the DC voltage into a second DC voltage having a second voltage. The modular-based DC/DC converter includes a modular power converter unit configured to generate the second DC voltage. The modular converter unit is configured to be independently interchangeable with a different modular converter unit.

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

Abstract: A method for providing a semiconductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

Abstract: A semiconductor structure having a semiconductor layer having an active device therein. A dielectric structure is disposed over the semiconductor layer, such dielectric structure having open ended trench therein. An electrical interconnect level is disposed in the trench and electrically connected to the active device. A plurality of stacked metal layers is disposed in the trench. The stacked metal layers have disposed on bottom and sidewalls thereof conductive barrier metal layers.

Abstract: A method for providing a semi conductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

Abstract: A semiconductor structure provided having: a dielectric; a non-column III-V doped semiconductor layer disposed over the dielectric; and an isolation barrier comprising column III-V material disposed vertically through the semiconductor layer to the dielectric. In one embodiment, the semiconductor layer is silicon and has CMOS transistors disposed in the semiconductor layer above a first region of the dielectric and a III-V transistor disposed above a different region of the dielectric. The barrier electrically isolates the column III-V transistor from the CMOS transistors. In one embodiment, the structure includes a passive device disposed over the semiconductor layer and a plurality of laterally spaced III-V structures, the III-V structures being disposed under the passive device, the III-V structures passing vertically through the semiconductor layer to the insulating layer.

Abstract: A structure is provided having: (A) a first silicon layer and a first silicon dioxide layer over the first silicon layer; and (B) a second silicon layer and a second silicon dioxide layer over the second silicon layer; the first silicon dioxide layer bonded to the second silicon dioxide layer. An upper surface of the first silicon layer is polished to reduce its thickness. A III-V layer is grown on the upper surface of the thinned silicon layer. A III-V device is formed in the III-V layer together with a strip conductor connected to the formed. The second silicon layer, the second silicon dioxide layer and the first silicon dioxide layer are successively removed to expose a bottom surface of the first silicon layer. A ground plane conductor is formed on the exposed bottom surface, the strip conductor and the ground plane conductor providing a microstrip transmission line.

Abstract: A structure is provided having: (A) a first silicon layer and a first silicon dioxide layer over the first silicon layer; and (B) a second silicon layer and a second silicon dioxide layer over the second silicon layer; the first silicon dioxide layer bonded to the second silicon dioxide layer. An upper surface of the first silicon layer is polished to reduce its thickness. A III-V layer is grown on the upper surface of the thinned silicon layer. A III-V device is formed in the III-V layer together with a strip conductor connected to the formed. The second silicon layer, the second silicon dioxide layer and the first silicon dioxide layer are successively removed to expose a bottom surface of the first silicon layer. A ground plane conductor is formed on the exposed bottom surface, the strip conductor and the ground plane conductor providing a microstrip transmission line.

Abstract: A method for depositing a column III-V material over a selected portion of a substrate through a window formed in a dielectric layer disposed over the selected portion of the substrate. The method includes forming a single crystal layer or polycrystalline layer over a field region of the dielectric layer adjacent to the window; and, growing, by MOCVD, column III-V material over the single crystal layer or polycrystalline layer and through the window over the selected portion of the substrate.