Patents by Inventor Jeng-Da Wu
Jeng-Da Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070128019Abstract: A blower includes a scroll housing and a damping rib. The scroll housing includes a body portion for guiding air, a hopper portion for discharging the air through an outlet, and a recess formed between the body portion and the hopper portion. The damping rib is adjacent to the recess connecting the body portion with the hopper portion to enhance structural integrity of the scroll housing.Type: ApplicationFiled: August 4, 2006Publication date: June 7, 2007Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHIH-HANG CHAO, YU-HSU LIN, JENG-DA WU
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Publication number: 20070076540Abstract: In one preferred embodiment, an objective lens actuator includes a base, a suspension apparatus mounted on the base, a holder suspended by the suspension apparatus for holding an objective lens, a voice coil motor (VCM) for driving the holder to vibrate, and a cover. The VCM includes a first yoke, a second yoke and a pair of magnets fixed on the first yoke and the second yoke respectively. The first yoke and the second yoke respectively include a first part and a second part. The cover is made of a material having a magnetic conductivity. The cover connects the first part and the second part of each of the first yoke and the second yoke.Type: ApplicationFiled: June 24, 2006Publication date: April 5, 2007Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHIH-HANG CHAO, YU-HSU LIN, JENG-DA WU, CHUN-MING CHEN
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Patent number: 7199479Abstract: A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps are formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.Type: GrantFiled: March 31, 2005Date of Patent: April 3, 2007Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Jeng-Da Wu
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Patent number: 7042078Abstract: A semiconductor package includes spacers, a chip, bonding wires, contacts, and an encapsulant. The chip is disposed on the spacers. The bonding wires are electrically connected to the chip, and the contacts are electrically connected to the bonding wires. The contacts are electrically connected to an external circuit board. The encapsulant encapsulates the spacers and the active and back surfaces of the chip so as to lower the thermal stress of the chip.Type: GrantFiled: February 12, 2004Date of Patent: May 9, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Jeng Da Wu
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Publication number: 20050275098Abstract: A conductive jointing structure that is applied on a chip with multitude of connection pads has a first conductive structure and a second conductive structure. The first conductive structure is allocated on one of the contact pads. The second conductive structure made of lead-free based material is consisted of multitude of stacked portions with respectively different modulus. The portion contacting the first conductive structure is with small modulus, while the portion away from the first conductive structure is with large modulus.Type: ApplicationFiled: June 14, 2005Publication date: December 15, 2005Inventor: Jeng-Da Wu
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Patent number: 6972489Abstract: A flip chip package with a thermometer comprises a chip, a substrate, and a thermocouple. The chip has an active surface and a plurality of bumps disposed on the active surface. The substrate defines a region for disposing the chip, and comprises a plurality of bump pads disposed on the region, corresponding to the bumps, and electrically connected to the bumps. Each of the thermocouples comprises a thermal contact which is disposed between the substrate and one of the bumps of the chip.Type: GrantFiled: August 13, 2003Date of Patent: December 6, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Jeng Da Wu, Ching Hsu Yang
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Publication number: 20050263883Abstract: An asymmetric bump structure for wafer is provided. First, the wafer includes multi-chip units each of which has an active surface. The asymmetric bump structure includes a conductive surface on the active surface, a conductive structure contacted the portion of the conductive surface and located on the both conductive surface and the active surface, and a conductive material contacted the conductive structure. The conductive material and the conductive structure contacted part of the conductive surface have respective geometric centers which are not on an identical vertical axis.Type: ApplicationFiled: May 20, 2005Publication date: December 1, 2005Inventors: Tong-Hong Wang, Yi-Shao Lai, Jeng-Da Wu
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Publication number: 20050236704Abstract: A chip package structure comprising a carrier, a chip and an underfill layer is disclosed. The carrier has a plurality of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip.Type: ApplicationFiled: April 27, 2005Publication date: October 27, 2005Inventor: Jeng-Da Wu
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Publication number: 20050230828Abstract: A chip package structure is provided. The chip package structure has a chip and a carrier, wherein the carrier has a package substrate and a plurality of contacts. The package substrate has a carrying surface and a back surface. The chip is disposed on the carrying surface of the package substrate, and the contacts are disposed on the back surface of the package substrate in a pattern of a plurality of concentric circles. Additionally, the chip package structure can be disposed on a circuit board with solder balls formed on the contacts to form a circuit board package structure. The thermal stress exerted on the solder balls may be uniformly distributed in the carrier, the chip package structure, and the circuit board package structure. The bonding strength between the package substrate and the circuit board is improved.Type: ApplicationFiled: April 15, 2005Publication date: October 20, 2005Inventor: Jeng-Da Wu
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Publication number: 20050224969Abstract: A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps are formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.Type: ApplicationFiled: March 31, 2005Publication date: October 13, 2005Inventor: Jeng-Da Wu
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Publication number: 20050224956Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.Type: ApplicationFiled: March 30, 2005Publication date: October 13, 2005Inventors: Chin-Li Kao, Yi-Shao Lai, Jeng-Da Wu, Tong-Hong Wang
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Publication number: 20050200014Abstract: A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 ?m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.Type: ApplicationFiled: January 17, 2005Publication date: September 15, 2005Inventors: William Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Chih-Huang Chang, Jeng-Da Wu, Wen-Pin Huang, Po-Jen Cheng
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Patent number: 6891274Abstract: An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 ?m to about 8 ?m.Type: GrantFiled: August 18, 2003Date of Patent: May 10, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: William Tze-You Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang, Po-Jen Cheng
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Patent number: 6864168Abstract: A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 ?m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.Type: GrantFiled: August 18, 2003Date of Patent: March 8, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: William Tze-You Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Chih-Huang Chang, Jeng-Da Wu, Wen-Pin Huang, Po-Jen Cheng
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Patent number: 6819002Abstract: An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable layer over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.Type: GrantFiled: August 18, 2003Date of Patent: November 16, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: William Tze-You Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang, Po-Jen Cheng
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Publication number: 20040212072Abstract: A semiconductor package comprises spacers, a chip, bonding wires, contacts, and an encapsulant. The chip is disposed on the spacers. The bonding wires are electrically connected to the chip, and the contacts are electrically connected to the bonding wires. The contacts are electrically connected to an external circuit board. The encapsulant encapsulates the spacers and the active and back surfaces of the chip so as to lower the thermal stress of the chip.Type: ApplicationFiled: February 12, 2004Publication date: October 28, 2004Inventor: Jeng Da Wu
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Publication number: 20040113273Abstract: An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 &mgr;m to about 8 &mgr;m.Type: ApplicationFiled: August 18, 2003Publication date: June 17, 2004Inventors: William Tze-You Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang, Po-Jen Cheng
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Publication number: 20040113272Abstract: A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 &mgr;m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.Type: ApplicationFiled: August 18, 2003Publication date: June 17, 2004Inventors: WILLIAM TZE-YOU CHEN, HO-MING TONG, CHUN-CHI LEE, SU TAO, CHIH-HUANG CHANG, JENG-DA WU, WEN-PIN HUANG, PO-JEN CHENG
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Publication number: 20040104484Abstract: An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.Type: ApplicationFiled: August 18, 2003Publication date: June 3, 2004Inventors: William Tze-You Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang, Po-Jen Cheng
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Publication number: 20040065949Abstract: A flip chip interconnect structure is formed on a bump pad of a chip, and includes an under bump metallurgy (UBM) formed on the bump pad, and a solder bump formed on the UBM. The solder bump includes tin and is further doped with metallic particles that are capable of reacting with tin in the solder bump to from an inter-metallic compound due to a thermal effect produced in use of a later fabrication process or an operation on the chip. Furthermore, the material of the metal particles is selected from a group consisting of copper, silver and nickel.Type: ApplicationFiled: May 6, 2003Publication date: April 8, 2004Inventors: William Tze-You Chen, Ho-Ming Tong, Chun-Chi Lee, Su Tao, Jeng-Da Wu, Chih-Huang Chang, Po-Jen Cheng