Abstract: The present disclosure relates to novel compounds for use in therapeutic treatment of a disease associated with peptidylarginine deiminases (PADs), such as peptidylarginine deiminase type 4 (PAD4). The present disclosure also relates to processes and intermediates for the preparation of such compounds, methods of using such compounds and pharmaceutical compositions comprising the compounds described herein.

Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

Abstract: A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.

Abstract: A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

Abstract: A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

Abstract: A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.

Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.

Abstract: Continuous time linear equalization devices are disclosed. A continuous time linear equalization device may include a first circuit including a first differential amplification element coupled to a first adjustable source degeneration element. The continuous time linear equalization device may also include a second circuit having an input coupled to an output of the first circuit and including a second differential amplification element coupled to a second adjustable source degeneration element. Systems are also disclosed.

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

Abstract: A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.

Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.

Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.

Abstract: A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.

Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.