Abstract: A semiconductor device fabrication method and resulting device in which a gate insulating film is formed on a semiconductor substrate, a gate electrode is formed on the gate insulating film, a gate cap is formed on the gate electrode, a heavy density impurity region is formed in the substrate and outside the gate electrode, first side walls are formed on sides of the gate electrode, the gate cap and the gate insulating film. The substrate outside the gate insulating film is etched down to a portion having a highest impurity density, and a light doping region surrounding the heavy impurity region is formed in the substrate. The method and resulting device prevents a hot carrier from being injected into a gate oxide film or a side wall, and reduces the generation of a junction current leakage and a short channel.

Abstract: Provided is a semiconductor device, including: a semiconductor substrate; a first conductive type well which is formed on the semiconductor substrate; first and second field oxide layers which are formed on the well, defining the active region of the device; a node junction, where second conductive type impurity ions are heavily doped, making contact with the field oxide layer in the well; a gate electrode formed by interposing a gate oxide layer between the second field oxide layer and the node junction on the well; a switching device made from an interlevel insulating layer, for covering the gate electrode, and having a contact hole exposing the node junction on the semiconductor substrate; a storage electrode which makes contact with the node junction through the contact hole; a dielectric layer formed on the storage electrode; and a memory device made of a plate electrode which is formed on the dielectric layer.

Abstract: A method for fabricating a bipolar device, including the steps of forming an epitaxial growth retarding layer on a substrate at a predetermined angle, forming a collector layer on the substrate so that the collector layer is adjacent the epitaxial growth retarding layer and has an inclined portion formed over an edge portion of the epitaxial growth retarding layer, forming a base layer having an inclined portion on the collector layer, and forming an emitter layer on the inclined portion of the base layer.

Abstract: A method for developing shallow trench isolation in a semiconductor device includes forming an ion diffusion area by implanting fluorine ions where a trench is to be formed in a semiconductor substrate before forming the trench, performing an annealing process or a tilt ion implantation process to diffuse the fluorine ions into both sides corresponding to the upper corners of the trench, wherein the fluorine implantation process increases the oxidation rate of the upper corners of the trench to be more than that of the semiconductor substrate when a light oxidation proceeds for preventing damage to the semiconductor substrate in forming the trench. Accordingly, the upper corner portions of the trench are formed to be rounded so as to distribute an electric field, thereby preventing a hump phenomenon when the completed semiconductor memory device is operated.

Abstract: A method for forming an isolating layer in a semiconductor device includes the steps of forming a first material layer on an active layer having a major axis and a minor axis, forming a second material layer in a form of sidewall at sides of the first material layer in a direction of the major axis, and conducting field oxidation using the first and second material layers as masks to form the isolating layer.

Abstract: A trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by the respective etching-back processes. Using the gate as a mask, a low concentration region for the LDD structure is formed. Using the gate and sidewall as a mask, a source region and a drain region are formed. Thus, the channel region makes a right angle with the trench or recess, and the channel region is bent. Further, the channel region is made to be formed so as to be longer than the width of the gate. Since the low concentration region for the LDD structure is formed only in the drain region, the source resistance can be decreased, and a gate with a narrow width can be easily formed. Further, even if the channel length is short, the occurrence of the DIBL phenomenon can be suppressed.

Abstract: A semiconductor device and fabrication method therefor which improve device operation of a CMOS device. The semiconductor device and fabrication method therefor prevent the deterioration of short channel properties of a PMOS device and improve current driving capability of an NMOS device. The semiconductor device has halo impurity regions formed in either the NMOS region or the PMOS region such that a channel length of the PMOS device. Also, the source channel length of the PMOS device. Also, the source and drain regions of the PMOS device are prevented from forming deep source and drain regions, thus, preventing deterioration of the short channel properties for the PMOS device.

Abstract: A MOSFET fabrication method which is capable of enhancing the reliability of a MOSFET by improving a short channel effect of a MOSFET, which includes the steps of forming an oxide possible film on a first buffer film on a substrate, isotropic etching the oxide possible film for exposing a portion of the first buffer film, forming a second buffer film by oxidizing the entire front surface of the substrate in order for the entire surface of the oxide possible film to be oxidized, forming a recess shape channel region formed in the substrate by a channel ion implantation into the resultant structure by using the second buffer film as a mask, removing the second buffer film, forming a gate on the channel region of the substrate, and forming a dopant ion implantation region in the substrate formed at both sides of the gate.

Abstract: A method for fabricating a CMOSFET includes the steps of forming a first well of a first conduction type and a second well of a second conduction type on a substrate of the first conduction type; forming gate electrodes having sides on the first well and the second well; forming semiconductor sidewall spacers of the first conduction type at the sides of the gate electrodes; forming a semiconductor layer of the second conduction type over the first well; implanting impurity ions of the first conduction type into the second well; and annealing the semiconductor substrate to form lightly doped shallow impurity regions of the first conduction type in the first and second wells under the semiconductor sidewall spacers, and heavily doped deep impurity regions of the second conduction type in the first well, and simultaneously activating the impurity ions in the second well to formed heavily doped deep impurity regions of the first conduction type in the second well.

Abstract: A metal oxide semiconductor field effect transistor includes source and drain regions formed between a gate. The gate comprises a first conductive layer and a second conductive layer formed on the first conductive layer, and the second conductive layer has curved sidewalls with an insulating layer formed adjacent to the sidewalls. The method of making such a transistor improves the fabrication process, since the deposition thickness is controlled rather than the amount of etching. The transistor has a shortened channel width with reduced overlap capacitance, and the LDD doping compensation phenomenon is removed.

Abstract: An area-variable varactor diode is disclosed, in which the capacitance can be arbitrarily varied under an applied bias voltage. The area-variable varactor diode is characterized in that, in order to ensure freedom to designing the epi-layer, to obtain the desired capacitance characteristics, and to facilitate the integration with other elements, a steeply varied depletion layer area is provided through a variation of the surface layout area, and thus, varied capacitance characteristics are obtained. In steeply varying the area of the depletion layer, an etching of the active layer, a selective epi-layer growth, and an ion implantation are carried out or a combination of them is carried out. The capacitance characteristics are varied in accordance with the pattern of the mask, and therefore, a restriction is not imposed on the epi-layer, with the result that an integration with other elements becomes easy.

Abstract: A fabrication method for a semiconductor memory device which remarkably improves a short-channel characteristic, and increases a driving electric current of the device by differently forming the thickness of side wall spacers formed at the sides of polysilicon gates in nMOS and pMOS regions, includes forming a gate insulating film on a semiconductor substrate having first and second regions, forming first and second gate electrodes in the first and second regions, respectively, on the substrate, forming a first conductive low concentration impurity area at the sides of the first gate electrode, forming a second conductive low concentration impurity area at the sides of the second gate electrode, forming a first insulating film on the substrate and a second insulating film on the first insulating film, stripping the second insulating film in the first region, forming first sidewall spacers at the sides of the first gate electrode, forming a first conductive high concentration impurity area in the substrate at