Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.

Abstract: Disclosed herein are a spalling-preventing composite material composed of fiber and powder, which have different diameters and melting points so as to be capable of realizing the effect of preventing spalling of high-strength concrete and the effect of improving the fluidity of concrete, and a high-strength refractory concrete comprising the spalling-preventing material. The composite material for preventing spalling of high-strength concrete is composed of powder and fiber at 1:1-3, wherein the powder is a polymer powder having a diameter of 0.10-0.5 mm and a melting point of 110-150° C., and the fiber is a conjugate fiber including a first fiber having a diameter of 0.05-0.10 mm, a length of 5-25 mm and a melting point of 150-190° C., and a second fiber having a diameter of 0.01-0.05 mm, a length of 5-25 mm and a melting point of 190-250° C., the first fiber being a polypropylene fiber, and the second fiber being a nylon fiber or a polyvinyl alcohol fiber.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract: A method for searching patent documents by applying degree of similarity and a system thereof are disclosed. The method for searching patent documents by applying degree of similarity comprises receiving at least one search keyword from a user of the service; searching a document previously stored in a database, by the search keyword; and evaluating a degree of similarity to the search keyword on the document that is searched by the search keyword, wherein the degree of similarity is evaluated by measuring at least one degree among a degree of appearance frequency of the search keyword in the document, a degree of proximity between the search keywords, and a degree of word order between the search keywords. Therefore, patent documents may be searched by arranging the documents according to a degree of similarity to a search keyword, and not according to whether the keyword is included in the patent documents.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A method of etching and cleaning objects contained in a vessel, includes etching the objects by providing etching solution into the vessel, forcing out the etching solution from the vessel by providing pressurized gas into the vessel; cleaning the objects by providing cleaning solution into the vessel; and draining the cleaning solution from the vessel. By forcing out the etching solution with a pressurized gas such as nitrogen gas, there is no density difference of the etching solution in contact with the objects, leading to uniform etching of the objects.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.

Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A method of searching an MP-MLQ fixed codebook through bit predetermination includes the steps of generating a target vector with amplitude, reducing time to search an optimal pulse array through the bit predetermination and searching all of pulses if two errors have an identical value.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: The multi functional cleaning module comprises a plurality of air curtain, an eximer ultraviolet light irradiating device, a brush, a high-speed shower device, and an air knife, where they are arranged continually on a plan and the glass substrates are inserted continually into them. The cleaning apparatus using the multi functional cleaning module comprises a driving part having a loading and an unloading portions as well as the multi functional cleaning module.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: The invention provides method of etching and cleaning objects contained in a vessel, including: etching the objects by providing etching solution into the vessel; exiting the etching solution from the vessel by providing pressurized gas into the vessel; cleaning the objects by providing cleaning solution into the vessel; and draining the cleaning solution from the vessel. By exiting the etching with pressurized gas such as nitrogen gas, there is no density difference of the etching solution through out the objects, leading to uniform etching of the objects.