Patents by Inventor Jeong-min Choi

Jeong-min Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140290747
    Abstract: The present disclosure provides a polymer capable of significantly improving the lifespan, efficiency, electrochemical stability and thermal stability of an organic solar cell, and an organic solar cell including a photoactive layer comprising the polymer.
    Type: Application
    Filed: February 5, 2013
    Publication date: October 2, 2014
    Inventors: Jinseck Kim, Jeong Min Choi, Jaesoon Bae, Jiyoung Lee
  • Publication number: 20140146614
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Nam-Kyeong Kim, Jeong-Min Choi
  • Publication number: 20140125926
    Abstract: There are provided a retardation film, a manufacturing method thereof, and a liquid crystal display device including the same. The retardation film includes 1) an acrylic film, 2) a coating layer of a negative C-type material, and 3) a primer layer including a copolymer containing an aromatic vinyl-based unit and a maleic acid-based unit, provided between the acrylic film and the coating layer of the negative C-type material. The retardation film may be used in an in-plane switching mode liquid crystal display device.
    Type: Application
    Filed: July 2, 2012
    Publication date: May 8, 2014
    Applicant: LG CHEM, LTD.
    Inventors: Jun-Wuk Park, Jeong-Min Choi, Nam-Jeong Lee
  • Publication number: 20140128546
    Abstract: There are provided a resin composition and an optical compensation film formed using the same, and more particularly, to a resin composition comprising (a) alkyl (meth)acrylate units, (b) styrene units, (c) 3 to 6 element heterocyclic units substituted with at least one carbonyl group and (d) vinyl cyanide units, and an optical film formed using the resin composition. Further, a resin composition according to the present invention can provide an optical film having excellent optical properties and superior optical transparency, less haze and superior mechanical strength and heat resistance simultaneously. Therefore, an optical film formed using a resin composition of the present invention can be used in various applications, e.g., electronic information devices such as display devices. Particularly, the optical film is suitable for a compensation film used in the IPS mode.
    Type: Application
    Filed: October 4, 2012
    Publication date: May 8, 2014
    Applicant: LG CHEM, LTD.
    Inventors: Jun-Geun Um, Jeong-Min Choi, Jun-Wuk Park, Nam-Jeong Lee
  • Patent number: 8642442
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Nam-Kyeong Kim, Jeong-Min Choi
  • Publication number: 20130032209
    Abstract: Disclosed herein are a 3,6-carbazle-containing copolymer, an organic solar cell comprising the copolymer in an organic material layer including a photoactive layer, and a method for fabricating the organic solar cell.
    Type: Application
    Filed: August 3, 2012
    Publication date: February 7, 2013
    Applicants: POSTECH ACADEMY-INDUSTRY FOUNDATION, LG CHEM, LTD.
    Inventors: Jinseok KIM, Jaechol LEE, Hangken LEE, Jeong Min CHOI, Jiyoung LEE, Taiho Park, Gang-Young LEE, Minjeong IM, Seulki SONG
  • Patent number: 8243239
    Abstract: The present invention relates to an in-plane switching (IPS) mode liquid crystal display. More particularly, the IPS mode liquid crystal display according to the present invention comprises 1) a first polarizing plate; 2) a liquid crystal cell; 3) a retardation film comprising a positive biaxial acryl-based film and a negative C plate; and 4) a second polarizing plate. Accordingly, a contrast property can be improved at a front side of the IPS mode liquid crystal display and at an inclining angle.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: August 14, 2012
    Assignee: LG Chem, Ltd.
    Inventors: Jeong-Min Choi, Min-Hee Lee, Sae-Han Cho
  • Publication number: 20120051129
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.
    Type: Application
    Filed: August 26, 2010
    Publication date: March 1, 2012
    Applicant: Numonyx B.V.
    Inventors: Nam-Kyeong Kim, Jeong-Min Choi
  • Patent number: 8120729
    Abstract: Disclosed is an optical film that is manufactured by using longitudinal and uniaxial stretching of an unstretched cycloolefin copolymer film and has an in-plane retardation of 100 to 150 nm and a thickness retardation of 0 to ?30 nm at a wavelength of 550 nm, a polarizing plate and a liquid crystal display including the same, and a method of manufacturing the optical film. The method includes longitudinally and uniaxially stretching the unstretched film while a ratio of a width to a length of a stretched portion of the film is controlled.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: February 21, 2012
    Assignee: LG Chem, Ltd.
    Inventors: Jeong-Min Choi, Kyung-Sik Kim, Min-Hee Lee, Jun-Geun Um, Sang-Min Kwak
  • Publication number: 20110262663
    Abstract: The present invention relates to a retardation film, a method for manufacturing the same, and a liquid crystal display device comprising the same. More particularly, the present invention relates to a retardation film which comprises 1) an acryl copolymer that comprises an acryl monomer and an aromatic vinyl monomer; and 2) a rubber component, and the retardation film according to the present invention has excellent optical transparency, haze, brittleness, mechanical strength, heat resistance and durability.
    Type: Application
    Filed: January 22, 2009
    Publication date: October 27, 2011
    Inventors: Jeong-Min Choi, Yoo-Seong Hong, Min-Hee Lee, Sang-Min Kwak, Jun-Geun Um, Kyung-Sik Kim
  • Publication number: 20110171441
    Abstract: The present invention provides a retardation film that comprises a) a first acrylic resin layer, and b) a second acrylic resin layer that is layered on at least one side of a) the first acrylic resin layer and comprises an acrylic resin and 1 to 20 parts by weight of rubber component based on 100 parts by weight of the acrylic resin. The retardation film according to the present invention has excellent optical transparency, haze, brittleness, mechanical strength, heat resistance, durability, and the like.
    Type: Application
    Filed: December 19, 2008
    Publication date: July 14, 2011
    Applicant: LG Chem, Ltd.
    Inventors: Jeong-Min Choi, Yoo-Seong Hong, Min-Hee Lee, Sang-Min Kwak, Jun-Geun Um, Kyung-Sik Kim
  • Patent number: 7723194
    Abstract: Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 25, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Min Choi, Tae-Hong Ha
  • Publication number: 20100073607
    Abstract: Disclosed is an optical film that is manufactured by using longitudinal and uniaxial stretching of an unstretched cycloolefin copolymer film and has an in-plane retardation of 100 to 150 nm and a thickness retardation of 0 to ?30 nm at a wavelength of 550 nm, a polarizing plate and a liquid crystal display including the same, and a method of manufacturing the optical film. The method includes longitudinally and uniaxially stretching the unstretched film while a ratio of a width to a length of a stretched portion of the film is controlled.
    Type: Application
    Filed: November 20, 2007
    Publication date: March 25, 2010
    Applicant: LG CHEM, LTD.
    Inventors: Jeong-Min Choi, Kyung-Sik Kim, Min-Hee Lee, Jun-Geun Um, Sang-Min Kwak
  • Publication number: 20100053508
    Abstract: The present invention relates to an in-plane switching (IPS) mode liquid crystal display. More particularly, the IPS mode liquid crystal display according to the present invention comprises 1) a first polarizing plate; 2) a liquid crystal cell; 3) a retardation film comprising a positive biaxial acryl-based film and a negative C plate; and 4) a second polarizing plate. Accordingly, a contrast property can be improved at a front side of the IPS mode liquid crystal display and at an inclining angle.
    Type: Application
    Filed: August 26, 2009
    Publication date: March 4, 2010
    Inventors: Jeong-Min Choi, Min-Hee Lee, Sae-Han Cho
  • Publication number: 20080268598
    Abstract: Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims.
    Type: Application
    Filed: July 3, 2008
    Publication date: October 30, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Min CHOI, Tae-Hong HA
  • Patent number: 7439593
    Abstract: Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Min Choi, Tae-Hong Ha
  • Publication number: 20080203913
    Abstract: A Plasma Display Panel (PDP) includes: a panel assembly having a first substrate, and a second substrate coupled to the first substrate; a chassis base coupled to the panel assembly, and supporting the panel assembly; and a foam adhesive member interposed between the panel assembly and the chassis base, and dissipating heat produced from the panel assembly. Since the porous foam adhesive member is interposed between the panel assembly and the chassis base, heat dissipation efficiency can be improved and image retention on a screen can be minimized.
    Type: Application
    Filed: September 27, 2007
    Publication date: August 28, 2008
    Inventors: Jung-Suk Song, Dong-Hyun Kim, Jeong-Min Choi, Jun-Tae Kim
  • Publication number: 20080186419
    Abstract: A plasma display device is provided having a plasma display panel, a chassis base arranged substantially parallel to the plasma display panel, a tape bonding the plasma display panel to the chassis base, and a radiative sheet interposed between and adhering to the plasma display panel and the chassis base. The radiative sheet is of material having a layered crystal structure. The layered crystal structure is arranged to extend at an angle from the plasma display panel. The angle is not horizontal/parallel to a surface of the plasma display panel.
    Type: Application
    Filed: August 8, 2007
    Publication date: August 7, 2008
    Inventors: Dong Hyun Kim, Young Soo Seo, Jung Suk Song, Jun Tae Kim, Jeong Min Choi
  • Publication number: 20080014703
    Abstract: A method of fabricating a semiconductor integrated circuit device may include forming a first gate insulating film and a first gate electrode on a first region of a substrate, and forming a second gate insulating film and a second gate electrode on which a plurality of recesses are formed on a second region of the substrate, forming first and second source/drain regions in the substrate, the first and second source/drain regions being aligned with the first and second gate electrodes, respectively, and forming a first metal silicide film and a second metal silicide film on the first and second source/drain regions and the second gate electrode, respectively, wherein the second metal silicide film is thicker than the first metal silicide film and a cross-sectional shape of the second metal silicide film is wave shaped.
    Type: Application
    Filed: July 9, 2007
    Publication date: January 17, 2008
    Inventor: Jeong-min Choi
  • Publication number: 20070094622
    Abstract: Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects. The first and second schematics are then combined at corresponding first and second ports within the first and second schematics, respectively. Operations also include generating an integrated circuit netlist by generating a circuit schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the post-layout interconnects. This circuit schematic is then combined with the first schematic at corresponding first and second ports therein.
    Type: Application
    Filed: November 28, 2006
    Publication date: April 26, 2007
    Inventors: Jong-bae Lee, Moon-hyun Yoo, Kyo-sun Kim, Jeong-min Choi