Abstract: A system and method is disclosed in which a circuit is provided to improve the settling performance of synthesizers used in read/write channel applications when the synthesizer is required to switch frequencies by a small percentage quickly. This is useful in read channel applications where the clock recovery is performed using an all-digital PLL. A digital timing recovery scheme is utilized in which one data frequency synthesizer provides both write and read frequencies. The read frequency is set higher than the write frequency to allow for oversampling when reading data from the storage medium. When changing from a write to read frequency or vice-versa the frequency synthesizer rapidly settles to the new frequency. The frequency synthesizer includes a phase locked loop which utilizes a controllable oscillator. The phase locked loop divisors are changed to obtain the desired frequency changes. An input signal to the controllable oscillator is also changed in order to obtain the rapid settling times.

Abstract: A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.

Abstract: An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.

Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

Abstract: A novel analog comparator having cascaded gain stages powered by two buses, the voltages on which are dependent on a reference input voltage. A network, responsive to the reference input voltage, sets the voltages on the buses and isolates the buses from external power and ground to achieve high power supply and ground noise immunity. An alternative design of the network is provided which removes errors in the accuracy of the comparator resulting from differing drain-to-source voltages across the various transistors. The accuracy of the comparator is then dependent on the accuracy of matching predetermined ratios of the sizes of the transistors.

Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

Abstract: A CMOS precision current source which is insensitive to changes in both ambient temperature and processing conditions. In particular, a CMOS circuit exhibits both a temperature dependent voltage (V(T)) and a temperature dependent on-chip resistance (R(T)) where the dependencies of both voltage and resistance are linear functions of temperature of the form y=mx+b. The ratio of the slopes (m.sub.V /m.sub.R) is constructed to be equal to the ratio of the y-intercepts (b.sub.v /b.sub.R), where this ratio is a constant value, denoted s. Therefore, since a constant output current I.sub.o is equal to V(T)/R(T), I.sub.o will be equal to the constant value s. Additionally, a constant reference voltage (V.sub.o) may also be provided with a minimal increase in the circuitry needed to provide the constant current.