Abstract: Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Abstract: Packet data received by a network controller is parsed and at least a portion of a received packet is stored by the network controller in both a host memory of a system and also in a cache memory of the central processing unit of the system. Other embodiments are described and claimed.