Patents by Inventor Jessica Hartwich
Jessica Hartwich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9352431Abstract: A device for forming a reduced chamber space, which is a process box or a process hood, containing an apparatus, which positions at least two multilayer bodies each including a surface to be processed, wherein the apparatus is designed such that the multilayer bodies are opposite to each other, wherein the surfaces to be processed are facing away from each other such that the multilayer bodies can be processed as a multilayer body arrangement in a processing system. In addition, a method for positioning the two multilayer bodies comprising a surface to be processed, with the two multilayer bodies disposed in such a device such that multilayer bodies are opposite each other, wherein the surfaces to be processed are facing away from each other, such that the multilayer bodies are processable as a multilayer body arrangement in a processing system.Type: GrantFiled: February 22, 2011Date of Patent: May 31, 2016Assignee: Saint-Gobain Glass FranceInventors: Joerg Palm, Stefan Jost, Martin Fuerfanger, Jessica Hartwich
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Publication number: 20130067723Abstract: A device for forming a reduced chamber space, which is a process box or a process hood, containing an apparatus, which positions at least two multilayer bodies each including a surface to be processed, wherein the apparatus is designed such that the multilayer bodies are opposite to each other, wherein the surfaces to be processed are facing away from each other such that the multilayer bodies can be processed as a multilayer body arrangement in a processing system. In addition, a method for positioning the two multilayer bodies comprising a surface to be processed, with the two multilayer bodies disposed in such a device such that multilayer bodies are opposite each other, wherein the surfaces to be processed are facing away from each other, such that the multilayer bodies are processable as a multilayer body arrangement in a processing system.Type: ApplicationFiled: February 22, 2011Publication date: March 21, 2013Applicant: SAINT-GOBAIN GLASS FRANCEInventors: Joerg Palm, Stefan Jost, Martin Fuerfanger, Jessica Hartwich
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Publication number: 20130059431Abstract: The present invention relates to a device for processing substrates in a processing system with at least one process tool disposed in at least one process area, which tool has two substrate levels disposed opposite each other in the process area, which are aligned at least approximately vertical, wherein the device is adapted to process at least two substrates at the same time in the process area by means of the process tool, wherein the substrates can be disposed in the substrate levels such that coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates. It further relates to a method for processing coated substrates in a processing system, wherein the substrates have coatings and the substrates are each disposed opposite each other such that the coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates.Type: ApplicationFiled: February 22, 2011Publication date: March 7, 2013Applicant: SAINT-GOBAIN GLASS FRANCEInventors: Jessica Hartwich, Franz Karg
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Patent number: 8124475Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.Type: GrantFiled: March 30, 2009Date of Patent: February 28, 2012Assignee: Infineon Technologies AGInventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rösner, Thomas Schulz
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Patent number: 7863136Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.Type: GrantFiled: September 30, 2008Date of Patent: January 4, 2011Assignee: Qimonda AGInventors: Matthias Goldbach, Jessica Hartwich, Lars Dreeskornfeld, Arnd Scholz, Tobias Mono
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Patent number: 7820505Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.Type: GrantFiled: September 27, 2007Date of Patent: October 26, 2010Assignee: Infineon Technologies, AGInventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rösner, Thomas Schulz
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Publication number: 20100078711Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: Qimonda AGInventors: Matthias Goldbach, Jessica Hartwich, Lars Dreeskornfeld, Arnd Scholz, Tobias Mono
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Patent number: 7622354Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.Type: GrantFiled: August 31, 2007Date of Patent: November 24, 2009Assignee: Qimonda AGInventors: Lars Dreeskornfeld, Jessica Hartwich, Tobias Mono, Arnd Scholz, Stefan Slesazeck
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Publication number: 20090184355Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.Type: ApplicationFiled: March 30, 2009Publication date: July 23, 2009Inventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rosner, Thomas Schulz
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Publication number: 20090086523Abstract: An integrated circuit comprises a memory cell array portion and a support circuitry portion. The memory cell array portion comprises at least one bitline and at least one wordline, which is disposed above the bitline. The support circuitry portion comprises a FinFET comprising a gate electrode. An upper side of a portion of the gate electrode is disposed at the same height as an upper side of a portion of the bitline. A method of manufacturing an integrated circuit comprises the steps of forming a memory cell array and forming a support circuitry. The step of forming the memory cell array comprises forming a bitline and forming a wordline disposed above the bitline. The step of forming the support circuitry comprises forming a FinFET. The step of forming the FinFET comprises forming a gate electrode, an upper side of a portion of the gate electrode being formed at the same height as an upper side of a portion of the bitline.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Jessica Hartwich, Lars Dreeskornfeld
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Publication number: 20090057778Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.Type: ApplicationFiled: August 31, 2007Publication date: March 5, 2009Inventors: Lars Dreeskornfeld, Jessica Hartwich, Tobias Mono, Arnd Scholz, Stefan Slesazeck
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Publication number: 20080296674Abstract: A transistor, an integrated circuit and a method of forming an integrated circuit is disclosed. One embodiment includes a gate electrode. The gate electrode is disposed in a gate groove formed in a semiconductor substrate and includes a conductive carbon material.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Applicant: QIMONDA AGInventors: Andrew Graham, Jessica Hartwich, Arnd Scholz
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Publication number: 20080299722Abstract: The present invention provides a method for forming a recessed channel transistor comprising the steps of: forming a plurality of active areas lines in a semiconductor substrate with an upper surface, said lines being segmented by segmentation structures having an upper surface height differing from the substrate surface; forming a first and a second extension region arranged above the active area and adjacent said segmentation structures; forming recessed channel devices in the active area segments in the remaining portion of the active area segment between said extension regions.Type: ApplicationFiled: May 29, 2007Publication date: December 4, 2008Inventors: Jessica Hartwich, Andrew Graham, Arnd Scholz, Yimin Wang, Stefan Slesazeck, Lars Heineck, Franz Hofmann
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Publication number: 20080283910Abstract: An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.Type: ApplicationFiled: May 15, 2007Publication date: November 20, 2008Applicant: QIMONDA AGInventors: Lars Dreeskornfeld, Dongping Wu, Jessica Hartwich, Juergen Holz, Arnd Scholz
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Publication number: 20080197384Abstract: A field effect transistor arrangement includes an electrically insulating layer, a source region, a drain region and a channel region arranged between source region and drain region, wherein the source region, the drain region and the channel region are in each case arranged on or above the electrically insulating layer, and also a gate region having an electrically insulating gate layer and an electrically conductive gate layer, which adjoins the channel region or is arranged at a distance from the latter and which extends at least partly along the channel region, wherein the source region and the drain region are in each case produced from electrically conductive carbon, and wherein the channel region is produced from strained silicon.Type: ApplicationFiled: February 21, 2008Publication date: August 21, 2008Inventors: Jessica Hartwich, Lars Dreeskornfeld, Gernot Steinlesberger
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Publication number: 20080038888Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.Type: ApplicationFiled: September 27, 2007Publication date: February 14, 2008Inventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rosner, Thomas Schulz
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Patent number: 7291877Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.Type: GrantFiled: October 10, 2003Date of Patent: November 6, 2007Assignee: Infineon Technologies, AGInventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rösner, Thomas Schulz
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Patent number: 7189988Abstract: The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor.Type: GrantFiled: July 1, 2002Date of Patent: March 13, 2007Assignee: Infineon Technologies AGInventors: Jessica Hartwich, Johannes Kretz, Richard Johannes Luyken, Wolfgang Rösner
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Patent number: 7173302Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.Type: GrantFiled: October 10, 2003Date of Patent: February 6, 2007Assignee: Infineon technologies AGInventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rösner, Thomas Schulz
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Publication number: 20060022302Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.Type: ApplicationFiled: October 10, 2003Publication date: February 2, 2006Inventors: Ralf Brederlow, Jessica Hartwich, Christian Pacha, Wolfgang Rosner, Thomas Schulz