Abstract: An exemplary system, method and computer-accessible medium for modifying a design of an integrated circuit(s) (ICs), which can include, for example, modifying a logic gate(s) in the design for a protected input pattern(s), and providing a restoration unit(s) into the design, where the restoration unit(s) can be configured to (i) produce an error-free output(s) when a correct secret key can be applied to the restoration unit(s), and (ii) produce an erroneous output(s) when an incorrect key can be applied to the restoration unit(s); and ensure that the modified design along with the restoration unit produces at least one erroneous output with respect to the original design for only a pre-determined constant number of incorrect keys based on at least one input pattern.

Abstract: Disclosed are various embodiments to enhance the security of a circuit design after a global routing of the circuit design and an assignment of wire layers for the circuit design. A tree can be extracted from the circuit design. The tree can include multiple gates and location information for the gates. The tree can be perturbed by moving one or more locations of one or more gates.

Abstract: Exemplary embodiments of the present disclosure can include an exemplary system, method and computer-accessible medium for camouflaging a design of an integrated circuit(s) (IC), can include, for example, receiving information related to a plurality of input combinations to the ICs, and camouflaging the design of the ICs by limiting a discriminating ability of the input combination to a predetermined constant number of incorrect assignments. An incorrect output can be intentionally produced for a predetermined constant number of secret minterms of the ICs. An output of the ICs can be restored for the secret minterms using a CamoFix block. The CamoFix block can include a CamoInputMapping block(s), a CamoSecGen block(s) or a comparator block(s).

Abstract: An exemplary system, method and computer-accessible medium can be provided which can include, for example, generating a super control dataflow graph(s) (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit, determining an upper bound(s) number and a lower bound(s) number based on a number of CDFGs in the super CDFG(s)—with each number being one metric of a capability of the integrated circuit to resist reverse engineering attack—, and inserting a component(s) into a register transfer level netlist to effectuate a modification of the upper bound(s) and the lower bound(s).

Abstract: Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit (“SARLock”), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).

Abstract: Exemplary systems, methods and computer-accessible mediums can secure split manufacturing of an integrated circuit by modifying a previous location of at least one pin to a further location of the at least one pin based on a fault analysis procedure. A determination of the further location can include an iterative procedure that can be a greedy iterative procedure. The modification of the location of the at least one partition pin can be performed by swapping at least one further partition pin with the at least one partition pin.

Abstract: An exemplary system, method and computer-accessible medium for modifying a design of an integrated circuit(s) (ICs), which can include, for example, modifying a logic gate(s) in the design for a protected input pattern(s), and providing a restoration unit(s) into the design, where the restoration unit(s) can be configured to (i) produce an error-free output(s) when a correct secret key can be applied to the restoration unit(s), and (ii) produce an erroneous output(s) when an incorrect key can be applied to the restoration unit(s); and ensure that the modified design along with the restoration unit produces at least one erroneous output with respect to the original design for only a pre-determined constant number of incorrect keys based on at least one input pattern.

Abstract: An exemplary system, method and computer-accessible medium for detecting the presence of a Trojan(s) in a circuit(s), can include, for example, receiving information related to a property(s) configured to determine the presence of the Trojan(s), and determining the presence of the Trojan(s) based on the property(s) and a design(s) of the circuit(s) using a bounded model checking tool.

Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Abstract: Disclosed are various embodiments to enhance the security of a circuit design after a global routing of the circuit design and an assignment of wire layers for the circuit design. A tree can be extracted from the circuit design. The tree can include multiple gates and location information for the gates. The tree can be perturbed by moving one or more locations of one or more gates.

Abstract: An exemplary system, method and computer-accessible medium for detecting the presence of a Trojan(s) in a circuit(s), can include, for example, receiving information related to a property(s) configured to determine the presence of the Trojan(s), and determining the presence of the Trojan(s) based on the property(s) and a design(s) of the circuit(s) using a bounded model checking tool.

Abstract: Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.

Abstract: Exemplary embodiments of the present disclosure can include an exemplary system, method and computer-accessible medium for camouflaging a design of an integrated circuit(s) (IC), can include, for example, receiving information related to a plurality of input combinations to the ICs, and camouflaging the design of the ICs by limiting a discriminating ability of the input combination to a predetermined constant number of incorrect assignments. An incorrect output can be intentionally produced for a predetermined constant number of secret minterms of the ICs. An output of the ICs can be restored for the secret minterms using a CamoFix block. The CamoFix block can include a CamoInputMapping block(s), a CamoSecGen block(s) or a comparator block(s).

Abstract: Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).

Abstract: An exemplary system, method and computer-accessible medium can be provided which can include, for example, generating a super control dataflow graph(s) (CDFG) by applying a plurality of electronic system level ESL design constraints associated with an integrated circuit, determining an upper bound(s) number and a lower bound(s) number based on a number of CDFGs in the super CDFG(s)—with each number being one metric of a capability of the integrated circuit to resist reverse engineering attack—, and inserting a component(s) into a register transfer level netlist to effectuate a modification of the upper bound(s) and the lower bound(s).

Abstract: Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.

Abstract: An exemplary system, method and computer-accessible medium for detecting the presence of a Trojan(s) in a circuit(s), can include, for example, receiving information related to a property(s) configured to determine the presence of the Trojan(s), and determining the presence of the Trojan(s) based on the property(s) and a design(s) of the circuit(s) using a bounded model checking tool.

Abstract: An exemplary system, method and computer-accessible medium for detecting the presence of a Trojan(s) in a circuit(s), can include, for example, receiving information related to a property(s) configured to determine the presence of the Trojan(s), and determining the presence of the Trojan(s) based on the property(s) and a design(s) of the circuit(s) using a bounded model checking tool.

Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Abstract: Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).