Patents by Inventor Jeyavijayan Rajendran

Jeyavijayan Rajendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160034628
    Abstract: Exemplary systems, methods and computer-accessible mediums can secure split manufacturing of an integrated circuit by modifying a previous location of at least one pin to a further location of the at least one pin based on a fault analysis procedure. A determination of the further location can include an iterative procedure that can be a greedy iterative procedure. The modification of the location of the at least one partition pin can be performed by swapping at least one further partition pin with the at least one partition pin.
    Type: Application
    Filed: March 14, 2014
    Publication date: February 4, 2016
    Inventors: JEYAVIJAYAN RAJENDRAN, OZGUR SINANOGLU, RAMESH KARRI
  • Patent number: 9081991
    Abstract: A ring oscillator (RO) based Design-For-Trust (DFTr) technique is described. Functional paths of integrated circuit (IC) are included in one or more embedded ROs by (1) selecting a path in the IC, based on path selection criteria, that has one or more unsecured gates, and (2) embedding one or more ROs on the IC until a stop condition is met. An input pattern to activate embedded RO is determined. Further, a golden frequency which is a frequency at which the embedded RO oscillates, and a frequency range of the embedded RO are determined. A Trojan in the IC may be detected by activating the embedded RO (by applying the input pattern), measuring a frequency at which the embedded RO oscillates, and determining whether or not a Trojan is present based on whether or not the measured frequency of the RO is within a predetermined operating frequency range of the RO.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 14, 2015
    Assignee: Polytechnic Institute of New York University
    Inventors: Vinayaka Jyothi, Ramesh Karri, Jeyavijayan Rajendran, Ozgur Sinanoglu
  • Patent number: 9081929
    Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: July 14, 2015
    Assignee: New York University
    Inventors: Ozgur Sinanoglu, Youngok Pino, Jeyavijayan Rajendran, Ramesh Karri
  • Publication number: 20120278893
    Abstract: A ring oscillator (RO) based Design-For-Trust (DFTr) technique is described. Functional paths of integrated circuit (IC) are included in one or more embedded ROs by (1) selecting a path in the IC, based on path selection criteria, that has one or more unsecured gates, and (2) embedding one or more ROs on the IC until a stop condition is met. An input pattern to activate embedded RO is determined. Further, a golden frequency which is a frequency at which the embedded RO oscillates, and a frequency range of the embedded RO are determined. A Trojan in the IC may be detected by activating the embedded RO (by applying the input pattern), measuring a frequency at which the embedded RO oscillates, and determining whether or not a Trojan is present based on whether or not the measured frequency of the RO is within a predetermined operating frequency range of the RO.
    Type: Application
    Filed: March 23, 2012
    Publication date: November 1, 2012
    Inventors: Vinayaka Jyothi, Ramesh Karri, Jeyavijayan Rajendran, Ozgur Sinanoglu