Patents by Inventor Jheng-Sheng YOU

Jheng-Sheng YOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180233577
    Abstract: A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is deposited over the contact metal layer, and an etch stop layer is deposited over the ARC layer. The etch stop layer, the ARC layer, and the contact metal layer are etched to form a contact stack over the III-V compound layer. A conductive layer is deposited over the III-V compound layer, and the conductive layer is etched to form a gate field plate. The etch stop layer has an etch selectivity different from that of the conductive layer.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 16, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng YOU, Hsin-Chih LIN, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU, Shen-Ping WANG, Chien-Li KUO
  • Patent number: 9985094
    Abstract: A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Lieh-Chuan Chen, Chih-Heng Shen, Po-Tao Chu
  • Patent number: 9941384
    Abstract: A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.
    Type: Grant
    Filed: August 29, 2015
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 9735232
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor substrate is received. A trench along a depth in the semiconductor substrate is formed. The semiconductor substrate is exposed in a hydrogen containing atmosphere. Dopants are inserted into a portion of the semiconductor substrate. A dielectric is filled in the trench. The dopants are driven into a predetermined distance in the semiconductor substrate.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-I Yang, Jheng-Sheng You, Chi-Fu Lin, Tien-Lu Lin
  • Patent number: 9698256
    Abstract: The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Lieh-Chuan Chen, Po-Tao Chu
  • Publication number: 20170062581
    Abstract: A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.
    Type: Application
    Filed: August 29, 2015
    Publication date: March 2, 2017
    Inventors: Jheng-Sheng YOU, Hsin-Chih LIN, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU, Shen-Ping WANG, Chien-Li KUO
  • Patent number: 9564515
    Abstract: A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu
  • Publication number: 20160087034
    Abstract: The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Lieh-Chuan Chen, Po-Tao Chu
  • Publication number: 20160027874
    Abstract: A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided.
    Type: Application
    Filed: July 28, 2014
    Publication date: January 28, 2016
    Inventors: Jheng-Sheng YOU, Che-Yi LIN, Shen-Ping WANG, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU
  • Publication number: 20150187872
    Abstract: A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jheng-Sheng YOU, Che-Yi LIN, Shen-Ping WANG, Lieh-Chuan CHEN, Chih-Heng SHEN, Po-Tao CHU
  • Publication number: 20150079771
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor substrate is received. A trench along a depth in the semiconductor substrate is formed. The semiconductor substrate is exposed in a hydrogen containing atmosphere. Dopants are inserted into a portion of the semiconductor substrate. A dielectric is filled in the trench. The dopants are driven into a predetermined distance in the semiconductor substrate.
    Type: Application
    Filed: July 24, 2014
    Publication date: March 19, 2015
    Inventors: Tai-I YANG, Jheng-Sheng YOU, Chi-Fu LIN, Tien-Lu LIN