Abstract: Embodiments of the present disclosure relate to a memory bit cell including two doped regions and four gate structures. Bit line, bit line bar, and word line of the bit cell are formed on a front side of the bit cell and power rails are formed on a back side of the bit cell. In some embodiments, each bit cell includes two word lines.

Abstract: A semiconductor structure includes a substrate, a dielectric wall, and two device units. The dielectric wall has two side surfaces opposite to each other. The two device units are respectively formed at the two side surfaces of the dielectric wall. Each of the device units includes channel features, a gate feature and a dielectric filler unit. The channel features are disposed on a corresponding one of the side surfaces of the dielectric wall, and spaced apart from each other. The gate feature is formed around the channel features and disposed on the corresponding one of the side surfaces of the dielectric wall. The dielectric filler unit includes a plurality of first dielectric fillers, each of which is disposed between the dielectric wall and a corresponding one of the channel features. The first dielectric fillers have a dielectric constant greater than that of the dielectric wall.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nanostructure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nanostructure may be formed as the thickest of the nanostructures in the vertical stack.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height different than the first cell height, a plurality of third logic cells having the first cell height, and a plurality of metal lines parallel to each other in a metal layer. Each of the first logic cells includes a plurality of multiple-fin transistors. Each of the second logic cells includes a plurality of single-fin transistors. Each of the third logic cells includes a plurality of single-fin transistors. The first logic cells and the third logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines inside the first and third logic cells are wider than the metal lines inside the second logic cells.

Abstract: A memory structure and a system-on chip (SOC) device are provided. A memory structure according to the present disclosure includes a first static random access memory (SRAM) macro comprising first gate-all-around (GAA) transistors and a second SRAM macro comprising second GAA transistors. The first GAA transistors of the first SRAM macro each includes a first plurality of channel regions each having a first channel width (W1) and a first channel thickness (T1). The second GAA transistors of the second SRAM macro each comprises a second plurality of channel regions each having a second channel width (W2) and a second channel thickness (T2). W2/T2 is greater than W1/T1.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A method of manufacturing a semiconductor device includes forming a first masking layer and second masking layer over a substrate. The first masking layer includes an opening over an active area and a spacer in the substrate, and the second masking layer having a block blocks a portion of the opening in the first masking layer. The block in the second masking layer has boundaries located completely within the boundary of the opening in the first masking layer. The method includes performing an etching process, using the first masking layer and the second masking layer as an etching mask, to form a contact opening which exposes a portion of the active area and a portion of the spacer, and forming a contact plug in the contact opening and over the exposed portion of the active area and the exposed portion of the spacer.

Abstract: A method includes forming a static random access memory (SRAM) array comprising a plurality of SRAM cells, at least one of the SRAM cells comprising first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors; forming a first front-side metal layer above the SRAM array, the first front-side metal layer comprising a first power supply voltage line and a bit-line, the first power supply voltage line electrically coupled to the first and second pull-up transistors, and the bit-line electrically coupled to the first pass-gate transistor; forming a back-side butt contact extending from a back-side of a gate structure of the first pull-up transistor to a back-side of a source/drain region of the second pull-up transistor from a cross sectional view.

Abstract: A memory device including a rectangular shaped via for at least one Vss node connection. In some embodiments, the rectangular shaped via has a length/width of greater than 1.5. The rectangular shaped via may be disposed on the Via0 and/or Via1 layer interfacing a first metal layer (e.g., M1). The memory cell may also include circular/square shaped vias having a length/width of between approximately 0.8 and 1.2. The circular/square shaped vias may be coplanar with the rectangular shaped vias.

Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.

Abstract: An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: Semiconductor structures and processes are provided that include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure may be formed on a dielectric wall from which nanostructure channel regions extend. The second gate isolation structure may be formed on a shallow trench isolation feature. The height of the first gate isolation structure is less than the height of the second gate isolation structure. The composition of the first gate isolation structure may be different than the composition of the second gate isolation structure. In some implementations, the first gate isolation structure is formed concurrently with gate spacers.

Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

Abstract: An integrated circuit device includes a first device and a second device. The first device is disposed within a first circuit region, the first device including a plurality of first semiconductor strips extending longitudinally in a first direction. Adjacent ones of the plurality of first semiconductor strips are spaced apart from each other in a second direction, which is generally perpendicular to the first direction. The second device is disposed within a second circuit region, the second circuit region being adjacent to the first circuit region in the first direction. The second device includes a second semiconductor strip extending longitudinally in the first direction. A projection of a longitudinal axis of the second semiconductor strip along the first direction lies in a space separating the adjacent ones of the plurality of first semiconductor strips.

Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.

Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

Abstract: A semiconductor structure includes a substrate and an array of two-port (TP) SRAM cells. Each TP SRAM cell includes a write port and a read port. The array includes first and second TP SRAM cells. The write ports of the first and second TP SRAM cells abut each other. The write port of the first TP SRAM cell includes a first write pull-down (W_PD) transistor. The write port of the second TP SRAM cell includes a second W_PD transistor. The array of TP SRAM cells further includes a first source/drain contact landing on both a source/drain electrode of the first W_PD transistor and another source/drain electrode of the second W_PD transistor. The first TP SRAM cell includes a first Vss conductor located at a first metal layer. The first Vss conductor is directly above the first source/drain contact and connected to the first source/drain contact.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes first channel members between a first and a second source/drain feature, a first gate structure wrapping around the first channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes second channel members between a third and a fourth source/drain features, a second gate structure wrapping around the second channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. A distance between the second gate spacer and the second source/drain contact is greater than a distance between the first gate spacer and the first source/drain contact.