Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.

Abstract: A memory device includes a first SRAM cell, a second SRAM cell, a write word line (WWL) landing line, and a Vdd line. The first SRAM cell and the second SRAM cell respectively include 8 transistors. The first WWL landing line is disposed inside a cell boundary of the first SRAM cell. The Vdd line is disposed in a cell boundary of the second SRAM cell. The first WWL landing line and the Vdd line are in a same layer.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first horizontal nanostructures formed over a substrate, and a plurality of second horizontal nanostructures adjacent to the first horizontal nanostructures. The semiconductor structure includes a dielectric wall formed between the first horizontal nanostructures and the second horizontal nanostructures. The semiconductor structure also includes a vertical nanostructure between the dielectric wall and the first horizontal nanostructures, and the vertical nanostructure is connected to and in direct contact with the dielectric wall. The semiconductor structure includes a gate structure surrounding the first horizontal nanostructures, the second horizontal nanostructures and the vertical nanostructure.

Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.

Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin having a first width doped with the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin having a second width doped with the first type dopant and second source/drain features of the first type dopant. The second width is greater than the first width. For example, a ratio of the second width to the first width is greater than about 1.1 and less than about 1.5.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.

Abstract: A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nano structure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nano structure may be formed as the thickest of the nanostructures in the vertical stack.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height, and a plurality of metal lines parallel to each other in a metal layer. The second cell height is different than the first cell height. The first logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines covering the first and second logic cells are wider than the metal lines inside the first logic cells, and the metal lines inside the first logic cells are wider than the metal lines inside the second logic cells.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.

Abstract: Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium.

Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A method includes receiving design data of a memory device; and generating a design layout including a first cell according to the design data. The first cell includes a first, a second, a third, and a fourth gate structures parallel to each other. The first cell further includes: a data storage element arranged including a first data node and a second data node, wherein the data storage element further comprises four transistors associated with the second and the third gate structures; a first access transistor and a second access transistor coupled to the first data node and the second data node, respectively; a first conductive line coupled to gate structures of the first access transistor and the second access transistor, respectively; and a second conductive line and a third conductive line each coupled to a source/drain region of the respective first and second access transistors.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: A method includes forming a doped region extending in a first direction on a substrate; depositing a gate electrode over the substrate and extending in a second direction; and forming a source/drain region on one side of the doped region; forming a first power rail over an upper surface of the source/drain region, the first power rail extending in the first direction and electrically coupled to the source/drain region; and depositing a second power rail below a lower surface of the source/drain region, the second power rail extending in the first direction and electrically coupled to the source/drain region. The first power rail overlap the second power rail from a top-view perspective.

Abstract: The static random access memory (SRAM) cell of the present disclosure includes a first pull-down device, a second pull-down device, a first pass-gate device, and a second pass-gate device in a first p-well on a substrate; a third pull-down device, a fourth pull-down device, a third pass-gate device, and a fourth pass-gate device in a second p-well on the substrate; a first pull-up device and a second pull-up device in an n-well between the first p-well and the second p-well; and a first landing pad between the second pull-down device and the first pull-up device. The first landing pad is electrically coupled to a gate structure of the second pass-gate device by way of a first gate via.

Abstract: A method of forming a semiconductor device includes forming first and second fin structures on a substrate, forming first and second gate stacks crossing the first and second fin structures, respectively, wherein the first fin structure has a first channel region under the first gate stack and a first source/drain region adjacent to the first channel region, and the second fin structure has a second channel region under the second gate stack and a second source/drain region adjacent to the second channel region, performing an ion implantation process to introduce impurities into the second source/drain region to form an implanted region in the second source/drain region, performing an etching process to form first and second recesses in the first and second source/drain regions, respectively, wherein the second recess penetrates through the implanted region, and forming epitaxy structures in the first and second recesses, respectively.

Abstract: An IC structure includes a first standard cell having a first pFET and a first nFET integrated; a first, second and third gates longitudinally oriented along a first direction and configured in the first standard cell; a first gate contact landing on the first gate and being adjacent two S/D contacts on two opposite edges of the first gate; a second gate contact landing on the second gate and being adjacent a single S/D contact on one edge of the second gate; and a third gate contact landing on the third gate and being free from any S/D contact. The first, second and third gate contacts span a first dimension D1, a second dimension D2, and a third dimension D3, respectively, along a second direction being orthogonal to the first direction. D1 is less than D2 and D2 is less than D3.