Patents by Inventor Ji-Soo Park

Ji-Soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160218173
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Inventors: Jie Bai, Anthony J. Lochtefeld, Ji-Soo Park
  • Publication number: 20160192341
    Abstract: Disclosed is a base station transmitting multiple beams to multiple beam areas, including: a determination unit determining at least any one of whether a downlink control signal is transmitted through the multiple beams transmitted to the multiple beam areas and a transmission section; a generation unit generating signal transmitting control information including at least any one of whether the downlink control signal is transmitted, the transmission section of the downlink control signal, and derivation information to derive a change of an access beam for a terminal that accesses the multiple beams; a communication unit downlink-transmitting the signal transmitting control information to the multiple beam areas or the multiple beams; and a control unit controlling transmission of the downlink control signal based on the signal transmitting control information.
    Type: Application
    Filed: December 30, 2015
    Publication date: June 30, 2016
    Inventors: Ji Soo PARK, Jun Woo KIM, Youn Ok PARK, Seung Jae BAHNG, Yong Su LEE
  • Patent number: 9365949
    Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ji-Soo Park
  • Patent number: 9318325
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Bai, Anthony J. Lochtefeld, Ji-Soo Park
  • Publication number: 20160049549
    Abstract: Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 18, 2016
    Inventor: Ji-Soo Park
  • Patent number: 9166107
    Abstract: Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Ji-Soo Park
  • Publication number: 20150108922
    Abstract: A motor driving device for a vehicle relates to a technology for preventing motor deterioration by controlling a stall current when a motor is controlled for vehicle air-conditioning. The motor driving device includes: a stall current detector that outputs a current detection signal by detecting a stall current of a motor, a controller that pre-stores a control specification of the motor, and outputs a control signal in response to the control specification when the current detection signal is activated; and an output driver that outputs a drive signal for controlling driving of the motor in response to the control signal.
    Type: Application
    Filed: December 26, 2013
    Publication date: April 23, 2015
    Applicants: Kia Motors Corporation, Hyundai Motor Company
    Inventors: Jin Kim, Young Su Kim, Yong Wook Kwon, Ji Soo Park
  • Publication number: 20150008441
    Abstract: Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material.
    Type: Application
    Filed: May 20, 2014
    Publication date: January 8, 2015
    Inventor: Ji-Soo Park
  • Publication number: 20140342536
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Inventors: Jie Bai, Anthony J. Lochtefeld, Ji-Soo Park
  • Publication number: 20140332850
    Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 13, 2014
    Inventor: Ji-Soo Park
  • Patent number: 8847279
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Bai, Ji-Soo Park, Anthony J. Lochtefeld
  • Publication number: 20140255968
    Abstract: The present invention relates to a method for fabricating a patterned substrate for a cell culture, comprising the steps of: (1) preparing a substrate; (2) depositing a plasma polymer layer by using a precursor material on the substrate; (3) placing a shadow mask having a predetermined pattern on the plasma polymer layer; (4) treating the substrate, having the shadow mask placed thereon, with a reactive gas using plasma; and (5) removing the shadow mask from the substrate, and a patterned substrate for the cell culture fabricated thereby. The invention also relates to a method for a cell culture with a pattern, comprising the step of culturing cells on the patterned substrate for the cell culture, and a patterned cell chip, and a method of screening a material having an activity of inducing or promoting angiogenesis using the patterned cell chip.
    Type: Application
    Filed: February 19, 2014
    Publication date: September 11, 2014
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Dong Geun JUNG, Myung Hoon HA, Heon Yong PARK, Ji Soo PARK, Hye Rim LEE
  • Patent number: 8822248
    Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ji-Soo Park
  • Patent number: 8729563
    Abstract: Solid state lighting (SSL) devices and methods are disclosed. A particular method includes forming an SSL formation structure having a CTE, selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material based at least in part on the second material having a CTE less than the first material CTE. The intelayer structure is formed over the SSL formation structure e.g., with a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The CTE difference between the first and second materials can counteract a force placed on the formation structure by the first material. Particular formation structures can have an off-cut angle with a non-zero value of up to about 4.5 degrees.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Ji-Soo Park
  • Patent number: 8462692
    Abstract: A system and method for reassembling packets in a packet relay node are provided. A packet relay node located between a transmitting node (i.e., a source node) and a receiving node (i.e., a destination node) inspects received packets to see if they are fragmented packets and reassembles a series of packets decided to be fragmented packets into an original packet, thereby reducing overhead and radio resource waste caused by duplicate transmission of IP headers having the same fragmented-packet information.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: June 11, 2013
    Assignees: Samsung Electronics Co., Ltd., Electronics and Telecommunications Research Institute
    Inventors: Ji-Soo Park, Cheol-Hye Cho, Sung-Hee Kim, Yeong-Jin Kim, Young-Jick Bahg
  • Patent number: 8436362
    Abstract: Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods are disclosed. A method in accordance with a particular embodiment includes forming an SSL (solid state lighting) formation structure having a formation structure coefficient of thermal expansion (CTE), selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material of the interlayer structure based at least in part on the second material having a second material CTE less than the first material CTE. The method can further include forming the interlayer structure over the SSL formation structure by disposing (at least) a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: May 7, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Ji-Soo Park
  • Publication number: 20130062615
    Abstract: Solid state lighting (SSL) devices and methods are disclosed. A particular method includes forming an SSL formation structure having a CTE, selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material based at least in part on the second material having a CTE less than the first material CTE. The intelayer structure is formed over the SSL formation structure e.g., with a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The CTE difference between the first and second materials can counteract a force placed on the formation structure by the first material. Particular formation structures can have an off-cut angle with a non-zero value of up to about 4.5 degrees.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 14, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Ji-Soo Park
  • Patent number: 8384196
    Abstract: Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, James Fiorenza, Jennifer M. Hydrick, Anthony J. Lochtefeld, Ji-Soo Park, Jie Bai, Jizhong Li
  • Publication number: 20120199876
    Abstract: Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.
    Type: Application
    Filed: April 13, 2012
    Publication date: August 9, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jie Bai, Ji-Soo Park, Anthony J. Lochtefeld
  • Patent number: 8208475
    Abstract: A method for scheduling packets from a plurality of radio bearers by a scheduler of a first layer includes calculating a virtual scheduling time for the radio bearers by using a packet delay variation of the radio bearers, and transmitting the packet of the radio bearer having the greatest virtual scheduling time from among the plurality of radio bearers to a second layer.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: June 26, 2012
    Assignees: Electronics and Telecommunications Research Institute, Samsung Electronics Co., Ltd.
    Inventors: Ji-Soo Park, Han-Jun Yoon, Dong-jin Shin, Cheol-Hye Cho, Moon-Soo Jang, Chang-Ki Kim, Young-Jick Bahg