Patents by Inventor Ji-Suk Kim
Ji-Suk Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240158822Abstract: Disclosed herein are a microorganism with excellent deacetoxycephalosporin C (DAOC) productivity and a use thereof. A mutant microorganism with improved DAOC productivity and a use thereof for producing 7-aminodeacetoxycephalosporanic acid (7-ADCA) are provided.Type: ApplicationFiled: October 17, 2023Publication date: May 16, 2024Inventors: Zhe PIAO, Young sung YUN, Hyeon Seo LEE, Yeon Hee CHOI, Mi Suk KANG, Xue Mei PIAO, You Mi KIM, Ji Su LEE, Hong Xian LI, Dong Il SEO, Dong Won JEONG, Seung Ki KIM
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Publication number: 20240153792Abstract: An apparatus and method for processing a substrate can reduce the concentration of process by-products in a chemical solution.Type: ApplicationFiled: November 7, 2023Publication date: May 9, 2024Applicants: SEMES CO., LTD., SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Jung KIM, Jin Ah HAN, Hee Hwan KIM, Yong Hoon HONG, Kyoung Suk KIM, Jong Hyeok PARK, Jin Hyung PARK, Dae Hyuk CHUNG, Ji Hoon CHA
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Publication number: 20240152724Abstract: The present invention provides a scalable digital twin system structure and a scalable digital twin service method that are capable of, based on a digital twin, performing real-time control of the real world while providing information required for the user to determine the optimal countermeasure in solve real-world problems in stages, thereby helping rapidly solve problems of the real-world. In order to preemptively respond to the real-world problems by providing decision support information with improved reliability according to a timeline based on a digital twin of a scalable structure, the operation of the digital twin is divided into several stages according to complexity and a result of each stage is transferred to an application service and the next stage, so that as the stage becomes higher, a more reliable result can be provided.Type: ApplicationFiled: November 7, 2022Publication date: May 9, 2024Inventors: Mi Suk LEE, Woo-Sug JUNG, Ji Eun KIM, Hyunjin KIM, Ki-Sook CHUNG
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Publication number: 20240121945Abstract: A semiconductor memory device comprises a substrate including a first source/drain region and a second source/drain region, a trench between the first source/drain region and the second source/drain region and formed in the substrate, a cell gate insulating layer on sidewalls and a bottom surface of the trench, a cell gate electrode on the cell gate insulating layer, a work function control pattern on the cell gate electrode, including N-type impurities and a cell gate capping pattern on the work function control pattern. The work function control pattern includes a semiconductor material. The work function control pattern includes a first region and a second region between the first region and the cell gate electrode. A concentration of the N-type impurities in the first region is greater than a concentration of the N-type impurities in the second region.Type: ApplicationFiled: July 6, 2023Publication date: April 11, 2024Inventors: Jin-Seong Lee, Tai Uk Rim, Ji Hun Kim, Kyo-Suk Chae
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Patent number: 11948487Abstract: The present disclosure provides a current mirror circuit including a first transistor configured to be supplied with a data current from a data driving circuit; a second transistor configured to drive a light emitting diode by mirroring the data current transferred to the first transistor; a capacitor disposed between the first transistor and the second transistor and configured to store a voltage of a gate terminal of the second transistor therein; and a first switch disposed between the first transistor and the second transistor and configured to adjust an input current of the gate terminal of the second transistor.Type: GrantFiled: September 9, 2022Date of Patent: April 2, 2024Assignee: LX SEMICON CO., LTD.Inventors: Ji Hwan Kim, Sang Suk Kim, Jang Su Kim
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Patent number: 11939308Abstract: The present disclosure provides a novel biphenyl derivative compound or a pharmaceutically acceptable salt thereof. The biphenyl derivative compound or pharmaceutically acceptable salt thereof according to the present disclosure is a compound that increases Nm23-H1/NDPK activity and can inhibit cancer metastasis and growth. Thus, it exhibits excellent effects not only on the prevention, alleviation and treatment of cancer, but also on the suppression of cancer metastasis.Type: GrantFiled: May 30, 2019Date of Patent: March 26, 2024Assignee: EWHA University—Industry Collaboration FoundationInventors: Kong Joo Lee, Hee-Yoon Lee, Je Jin Lee, Hwang Suk Kim, Ji-Wan Seo, Hongsoo Lee, Ji Soo Shin, Bo-kyung Kim
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Patent number: 11912674Abstract: The present invention provides methods for treating or ameliorating metabolic diseases, cholestatic liver diseases, or organ fibrosis, which comprises administering to a subject a therapeutically effective amount of a pharmaceutical composition comprising an isoxazole derivative, a racemate, an enantiomer, or a diastereoisomer thereof, or a pharmaceutically acceptable salt of the derivative, the racemate, the enantiomer, or the diastereoisomer.Type: GrantFiled: March 4, 2021Date of Patent: February 27, 2024Assignee: IL DONG PHARMACEUTICAL CO., LTD.Inventors: Jae-Hoon Kang, Hong-Sub Lee, Yoon-Suk Lee, Jin-Ah Jeong, Sung-Wook Kwon, Jeong-Guen Kim, Kyung-Sun Kim, Dong-Keun Song, Sun-Young Park, Kyeo-Jin Kim, Ji-Hye Choi, Hey-Min Hwang
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Publication number: 20220316982Abstract: The present invention provides a load generating unit for testing an actuator, the unit including a first permanent magnet and a second permanent magnet spaced apart from each other; a third permanent magnet or a ferromagnetic body arranged in a row with the first permanent magnet and the second permanent magnet between the first permanent magnet and the second permanent magnet; and a first link passing through central axes of the first permanent magnet and the second permanent magnet to be penetrated to a central axis of the third permanent magnet and be connected to the actuator, wherein the third permanent magnet and the link are displaced in a length direction of the first link by a magnetic force. According to the present invention, the complexity, cost, and inertia of a device may be overcome and a load profile may be easily generated.Type: ApplicationFiled: March 29, 2022Publication date: October 6, 2022Inventors: Seung-Chul HAN, Ji-Suk KIM, Ha-Jun LEE, Dae-Gyeom KANG
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Patent number: 11227659Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: GrantFiled: September 15, 2020Date of Patent: January 18, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
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Patent number: 11062775Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: GrantFiled: April 13, 2020Date of Patent: July 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
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Publication number: 20200411103Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: ApplicationFiled: September 15, 2020Publication date: December 31, 2020Inventors: BONGSOON LIM, JUNG-YUN YUN, JI-SUK KIM, SANG-WON PARK
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Publication number: 20200243140Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: BONGSOON LIM, JUNG-YUN YUN, JI-SUK KIM, SANG-WON PARK
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Patent number: 10658040Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.Type: GrantFiled: November 15, 2016Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
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Patent number: 10635532Abstract: A method for controlling error check and correction (ECC) of a non-volatile memory device includes storing write data in a plurality of storing regions. The write data may be generated by performing ECC encoding. Individual ECC decoding may be performed based on each of a plurality of read data read out from the storing regions. Logic operation data may be provided by performing a logic operation of the read data when the individual ECC decoding fails with respect to all of the read data. Combined ECC decoding may be performed based on the logic operation data.Type: GrantFiled: February 21, 2018Date of Patent: April 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Suk Kim, Sang-In Park, Il-Han Park, Sang-Yong Yoon, Gyu-Seon Rhim, Sung-Woon Choi
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Patent number: 10346097Abstract: A storage device includes a nonvolatile memory device and a controller configured to send first data, an address, and a first command to the nonvolatile memory device. The controller also sends at least one data to the nonvolatile memory device after sending the first command. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the first command. When receiving the at least one data from the controller, the nonvolatile memory device is configured to continue to perform the program operation based on the first data and the at least one data.Type: GrantFiled: November 23, 2016Date of Patent: July 9, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Suk Kim, Jung-Yun Yun, Bongsoon Lim
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Publication number: 20190026181Abstract: A method for controlling error check and correction (ECC) of a non-volatile memory device includes storing write data in a plurality of storing regions. The write data may be generated by performing ECC encoding. Individual ECC decoding may be performed based on each of a plurality of read data read out from the storing regions. Logic operation data may be provided by performing a logic operation of the read data when the individual ECC decoding fails with respect to all of the read data. Combined ECC decoding may be performed based on the logic operation data.Type: ApplicationFiled: February 21, 2018Publication date: January 24, 2019Inventors: Ji-Suk KIM, Sang-In PARK, IL-Han PARK, Sang-Yong YOON, Gyu-Seon RHIM, Sung-Woon CHOI
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Patent number: 10008270Abstract: A programming method of a non-volatile memory device including a plurality of memory cells arranged in a plurality of cell strings includes sequentially applying a first pass voltage to unselected word lines of word lines connected to the plurality of memory cells during a first interval and a second pass voltage higher than the first pass voltage to the unselected word lines during a second interval; and applying a discharge voltage lower than a program voltage to a selected word line of the word lines connected to the plurality of memory cells after applying the program voltage to the selected word line in the first interval, and applying the program voltage to the selected word line during the second interval.Type: GrantFiled: December 19, 2016Date of Patent: June 26, 2018Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Yo-han Lee, Ji-suk Kim, Chang-yeon Yu, Jin-young Chun, Se-heon Baek, Jun-young Ko, Seong-ook Jung, Ji-su Kim
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Patent number: 9978458Abstract: A data read operation method of a memory device includes applying a read voltage having a first preparation level and a first target level to a word line of a selected cell in the memory device to read a program state of the selected cell, applying a first read pass voltage having a second preparation level and a second target level to at least one word line of first non-selected cells not adjacent to the selected cell and in the same string as the selected cell, and applying a second read pass voltage having a third target level to a word line of at least one second non-selected cell adjacent to the selected cell.Type: GrantFiled: December 19, 2016Date of Patent: May 22, 2018Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Yo-han Lee, Ji-suk Kim, Chang-yeon Yu, Jin-young Chun, Se-heon Baek, Jun-young Ko, Seong-ook Jung, Ji-su Kim
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Publication number: 20170287561Abstract: A programming method of a non-volatile memory device including a plurality of memory cells arranged in a plurality of cell strings includes sequentially applying a first pass voltage to unselected word lines of word lines connected to the plurality of memory cells during a first interval and a second pass voltage higher than the first pass voltage to the unselected word lines during a second interval; and applying a discharge voltage lower than a program voltage to a selected word line of the word lines connected to the plurality of memory cells after applying the program voltage to the selected word line in the first interval, and applying the program voltage to the selected word line during the second interval.Type: ApplicationFiled: December 19, 2016Publication date: October 5, 2017Applicants: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: YO-HAN LEE, Ji-suk KIM, Chang-yeon YU, Jin-young CHUN, Se-heon BAEK, Jun-young KO, Seong-ook JUNG, Ji-su KIM
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Publication number: 20170278579Abstract: A data read operation method of a memory device includes applying a read voltage having a first preparation level and a first target level to a word line of a selected cell in the memory device to read a program state of the selected cell, applying a first read pass voltage having a second preparation level and a second target level to at least one word line of first non-selected cells not adjacent to the selected cell and in the same string as the selected cell, and applying a second read pass voltage having a third target level to a word line of at least one second non-selected cell adjacent to the selected cell.Type: ApplicationFiled: December 19, 2016Publication date: September 28, 2017Applicants: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: YO-HAN LEE, Ji-suk KIM, Chang-yeon YU, Jin-young CHUN, Se-heon BAEK, Jun-young KO, Seong-ook JUNG, Ji-su KIM