Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

Abstract: The present disclosure relates to a heat transfer tube comprising nanostructures formed on the surface, and a method for manufacturing the same, and by forming nanostructures on a heat transfer tube surface, a superhydrophobic surface may be obtained under a high temperature environment as well. In addition, superhydrophobicity may be enhanced by further forming a hydrophobic coating layer on the nanostructure-formed heat transfer tube surface. By using a method of forming nanostructures by dipping the heat transfer tube surface, complex shapes may be coated, and therefore, a plurality of assembled heat transfer tubes may be coated, and damages occurring during a process of assembling the heat transfer tube after coating may be prevented.

Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

Abstract: The present disclosure relates to a heat transfer tube having rare-earth oxide deposited on a surface thereof and a method for manufacturing the same, in which the rare-earth oxide can be deposited on the surface of the heat transfer tube to implement a superhydrophobic surface even under the high temperature environment and a plurality of assembled heat transfer tubes can be coated by coating a complex shape by depositing rare-earth oxide using a method for dipping a surface of the heat transfer tube and coating the same, thereby reducing or preventing the heat transfer tubes from being damaged during the assembling of the heat transfer tubes after the coating.

Abstract: Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

Abstract: Provided herein are a novel Zn-DPA complex compound and an siRNA delivery system including the same as a transporter, the Zn-DPA complex compound including: a phosphate-directing functional part of zinc (II)-dipicolylamine (“Zn-DPA”); a cell membrane-directing functional part; and a linker part that links the phosphate-directing functional part and the cell membrane-directing functional part. The Zn-DPA complex compound has low toxicity and efficiently delivers siRNA to cells, thereby useful in various ways for various studies and diagnosis and treatment of diseases, which use siRNA.

Abstract: A system for coating a heat transfer tube for a condenser is disclosed. The system simplifies a process of coating the heat transfer tube, and is able to uniformly coat a plurality of heat transfer tubes. In addition, the system is economically feasible in that coating solution can be reused by collecting and circulating it. Due to super-hydrophobic coating, the size of a droplet condensed on the surfaces of the heat transfer tubes coated by the system can be reduced, and a condensation heat transfer coefficient can be increased.

Abstract: A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Abstract: A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.