Abstract: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when the multi-level flash memory cells are further programmed. Where an error or malfunction occurs during the further programming of the multi-level flash memory cells, the backup copy of the previously programmed data is used to program different multi-level flash memory cells.

Abstract: A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection.

Abstract: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: A memory system includes a flash memory storing multi-bit data in one memory cell. A memory controller controls the flash memory to program the multi-bit data in the memory cell. The flash memory programs the multi-bit data in the memory cell in a single program operation.

Abstract: A method of programming a multilevel cell flash memory includes dividing a memory cell array of the flash memory into a user block and a cache block, programming first LSB data into a page of the user block, programming first MSB data into the page of the user block after programming the first LSB data, programming second LSB data into a page of the cache block, and storing control data for controlling the flash memory in the cache block.

Abstract: Provided are a memory system and a program method. The memory system includes a flash memory and a memory controller. The flash memory stores first bit data and then stores second bit data in a multi-level memory cell. The memory controller includes a buffer memory temporarily storing the first bit data and the second bit data, and a backup memory storing the first bit data while the flash memory is storing the second bit data. The backup memory re-programs the first bit data to the flash memory upon detecting a program failure associated with the storing the second bit data.

Abstract: A data storage circuit and a data preservation method for preserving data when a semiconductor device is in a sleep mode using a test scan chain are provided, where the data storage circuit includes a sleep mode control unit and a scan chain unit, the sleep mode control unit outputs a scan control signal and a scan clock signal in response to one of a test control signal and a sleep mode control signal received from the outside, stores an output data signal in a memory when the output data signal is received, and outputs a test pattern data signal as a scan data signal when the test pattern data signal is received, the scan chain unit outputs a normal data signal stored inside of the scan chain unit as the output data signal to the sleep mode control unit or receives and outputs the scan data signal to a combinational circuit unit in response to the scan control signal and the scan clock signal, and the data storage circuit and the data preservation method prevent a loss of data in a sleep mode of a semicondu

Abstract: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level flash memory cells fails. The backup copy of the previously programmed data is used to detect and correct any errors in the previously programmed data before reprogramming the previously programmed data to different multi-level memory cells in the nonvolatile memory system.

Abstract: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when the multi-level flash memory cells are further programmed. Where an error or malfunction occurs during the further programming of the multi-level flash memory cells, the backup copy of the previously programmed data is used to program different multi-level flash memory cells.

Abstract: A memory card includes a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: A memory card comprises a non-volatile memory; and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory. The power management unit boosts/bypasses the external supply voltage based on whether the external supply voltage is lower than a detection voltage and then outputs the boosted/bypassed voltage as the operating voltage of the non-volatile memory.

Abstract: A semiconductor device comprises a multilayer formed on a semiconductor substrate, the multilayer including a first circuit pattern, a second circuit pattern for testing the semiconductor device, the second circuit formed on a predetermined region of the multilayer, an inter-metal insulating layer formed on the second circuit pattern, a plurality of via contacts formed in the inter-metal insulating layer, and a plurality of ROM interface pads disposed on the inter-metal insulating layer, wherein the plurality of ROM interface pads are electrically connected with the second circuit pattern through the plurality of via contacts, and are separated from one another.

Abstract: A memory card including a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the external supply voltage is lower than a detection voltage, the power management unit boosts the external supply voltage and outputs the boosted voltage as the operating voltage of the non-volatile memory.

Abstract: A data storage circuit and a data preservation method for preserving data when a semiconductor device is in a sleep mode using a test scan chain are provided, where the data storage circuit includes a sleep mode control unit and a scan chain unit, the sleep mode control unit outputs a scan control signal and a scan clock signal in response to one of a test control signal and a sleep mode control signal received from the outside, stores an output data signal in a memory when the output data signal is received, and outputs a test pattern data signal as a scan data signal when the test pattern data signal is received, the scan chain unit outputs a normal data signal stored inside of the scan chain unit as the output data signal to the sleep mode control unit or receives and outputs the scan data signal to a combinational circuit unit in response to the scan control signal and the scan clock signal, and the data storage circuit and the data preservation method prevent a loss of data in a sleep mode of a semicondu

Abstract: A memory card comprises a non-volatile memory and a power management unit for receiving an external supply voltage to supply an operating voltage to the non-volatile memory, wherein when the external supply voltage is lower than a detection voltage, the power management unit boosts the external supply voltage and outputs the boosted voltage as the operating voltage of the non-volatile memory.

Abstract: An address counter and address counting method is provided for enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external address or a previous internal address is inputted and further generating both a path for the case when a parity signal having a high state is inputted and a path for the case when a parity signal having a low state is inputted. While the paths are being produced, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Moreover, an operation of latching the next address is terminated as soon as the parity signal is generated.

Abstract: The present invention relates to the field of the semiconductor fabrication. Also, the objects of the present invention are to provide a semiconductor device and method for fabricating the same having the MOS transistors capable of improving the thermal conduction characteristics and the punch-through and the DIBL effect. To accomplish these objects, the present invention provides the semiconductor device including a semiconductor substrate; a first insulating layer, a selected material layer and a second insulating layer orderly stacked on said semiconductor substrate; and a semiconductor layer formed on the second insulating layer for providing an active area where MOS transistors are formed, wherein, said material layer provides a path for emitting heat generated from said MOS transistors.

Abstract: A semiconductor memory device having a word line enable sensing block for driving sense amplifiers only when a word line is enabled. In this way, an enable time point of the sense amplifiers is controlled according to variations in operating conditions such as a temperature, process, voltage and size of a memory cell. In addition, the semiconductor memory device can embody an embedded memory logic.

Abstract: A dynamic random access memory(DRAM) cell having no capacitor, comprising: a silicon layer doped with impurities of a first conductivity type; a metal oxide semiconductor (MOS) transistor having a gate formed on one surface of the silicon layer and a source and drain regions formed in the silicon layer, the source and the drain regions being doped with impurities of a second conductivity type to induce channel the silicon layer under the gate; an insulating layer formed on another surface of the silicon layer; a conduction layer for a plate electrode formed on the insulating layer; and a purge region formed in the silicon layer to purge minor carriers induced in an interface surface between the silicon layer and the insulating layer, the purge region doped with impurities of the first conductivity type.