Abstract: The present invention relates to the field of the semiconductor fabrication. Also, the objects of the present invention are to provide a semiconductor device and method for fabricating the same having the MOS transistors capable of improving the thermal conduction characteristics and the punch-through and the DIBL effect. To accomplish these objects, the present invention provides the semiconductor device including a semiconductor substrate; a first insulating layer, a selected material layer and a second insulating layer orderly stacked on said semiconductor substrate; and a semiconductor layer formed on the second insulating layer for providing an active area where MOS transistors are formed, wherein, said material layer provides a path for emitting heat generated from said MOS transistors.

Abstract: A semiconductor memory device having a word line enable sensing block for driving sense amplifiers only when a word line is enabled. In this way, an enable time point of the sense amplifiers is controlled according to variations in operating conditions such as a temperature, process, voltage and size of a memory cell. In addition, the semiconductor memory device can embody an embedded memory logic.

Abstract: There is provided an address counter and address counting method capable of enhancing an operational speed by forming a path for outputting a corresponding output address as soon as an external address or a previous internal address is inputted and further generating both of a path for the case a parity signal having a high state is inputted and that for the case the parity signal having a low state is provided. At the same time of producing the paths, the parity signal is generated and the next internal address is immediately outputted in response to the generation of the parity signal. Moreover, an operation of latching the next address is terminated as soon as the parity signal is generated.

Abstract: The present invention relates to the field of the semiconductor fabrication. Also, the objects of the present invention are to provide a semiconductor device and method for fabricating the same having the MOS transistors capable of improving the thermal conduction characteristics and the punch-through and the DIBL effect. To accomplish these objects, the present invention provides the semiconductor device including a semiconductor substrate; a first insulating layer, a selected material layer and a second insulating layer orderly stacked on said semiconductor substrate; and a semiconductor layer formed on the second insulating layer for providing an active area where MOS transistors are formed, wherein, said material layer provides a path for emitting heat generated from said MOS transistors.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel.

Abstract: A semiconductor memory device arrangement that provides improved sensitivity of a sense amplifier that reads data from a memory cell. This sensitivity increase is accomplished by increasing a voltage difference between a data I/O line an a complementary data I/O line. A plurality of memory cells stor data. A data input/output (I/O) line pair (including a data I/O line and a complementary data I/O line), coupled to the memory cells, transfers the data. A sense amplifier senses and amplifies a voltage difference between the data I/O line and the complementary data I/O line. A capacitor has a first of its terminals coupled to the data I/O line. A first switching unit transfers the data applied to the data I/O line pair to two terminals of the capacitor in response to a first control signal. A second switching unit couples the second terminal of the capacitor to the data I/O line in response to a second control signal.

Abstract: A semiconductor memory device arrangement that provides improved sensitivity of a sense amplifier that reads data from a memory cell. This sensitivity increase is accomplished by increasing a voltage difference between a data I/O line an a complementary data I/O line. A plurality of memory cells stor data. A data input/output (I/O) line pair (including a data I/O line and a complementary data I/O line), coupled to the memory cells, transfers the data. A sense amplifier senses and amplifies a voltage difference between the data I/O line and the complementary data I/O line. A capacitor has a first of its terminals coupled to the data I/O line. A first switching unit transfers the data applied to the data I/O line pair to two terminals of the capacitor in response to a first control signal. A second switching unit couples the second terminal of the capacitor to the data I/O line in response to a second control signal.

Abstract: The present invention relates to a semiconductor memory device; and, more particular, to DRAM and SRAM having a common pin for address and data signals. A semiconductor memory circuit in accordance with the present invention has at least one common signal input terminal for receiving data signals and address signals, wherein the common signal input terminal is coupled to a plurality signal paths and a signal path selector for selecting one of the plurality signal paths in response to a write enable signal, a read enable and a control signal from a memory controller. The signal path selector has a plurality of buffers on the signal paths and the signal path selector selects one of the buffers in response to a write enable signal, a read enable and a control signal from a memory controller.

Abstract: A repair circuit of a semiconductor memory device includes a programming circuit operating independently from a high voltage supply, to replace a defective cell with a redundant cell using an anti-fuse, by generating a repair value based on an address signal being input to the memory device.

Abstract: A dynamic random access memory(DRAM) cell having no capacitor, comprising: a silicon layer doped with impurities of a first conductivity type; a metal oxide semiconductor (MOS) transistor having a gate formed on one surface of the silicon layer and a source and drain regions formed in the silicon layer, the source and the drain regions being doped with impurities of a second conductivity type to induce channel in the silicon layer under the gate; an insulating layer formed on another surface of the silicon layer; a conduction layer for a plate electrode formed on the insulating layer; and a purge region formed in the silicon layer to purge minor carriers induced in an interface surface between the silicon layer and the insulating layer, the purge region doped with impurities of the first conductivity type.

Abstract: A semiconductor device having an adjacent P-well and N-well, such as a complementary metal oxide semiconductor (CMOS) transistor, on a silicon on insulator (SOI) substrate has a latch-up problem caused by the parasitic bipolar effect. This invention provides a semiconductor device removing the latch-up problem and methods for fabricating the same. A semiconductor device according to the present invention has a T-shaped field oxide layer connected to a buried oxide layer of the SOI substrate to prevent the latch-up problem.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel.