Abstract: Provided is a zinc-plated steel sheet for hot pressing having outstanding surface characteristics, comprising: a steel foundation plate comprising a metal surface diffusion layer of which the Gibbs free energy reduction per mole of oxygen during oxidation is less than that of Cr; an aluminum-rich layer containing at least 30 wt. % of aluminium formed on the surface diffusion layer, and a zinc plating layer formed on the aluminum-rich layer. In this way, a metal having a low affinity for oxygen is coated to an effective thickness prior to annealing and thus the creation of annealing oxides at the surface of the steel sheet is suppressed and a uniform zinc plating layer is formed, and alloying of the zinc plating layer is promoted during press-processing heat treatment. Cracking in the steel foundation plate during hot press molding is prevented.

Abstract: Provided are a high strength thin steel sheet having tensile strength of about 800 MPa or more, and a manufacturing method thereof. The thin steel sheet is mainly used for construction materials, home appliances, and automobiles. The thin steel sheet has excellent plating characteristic, welding characteristic, bending workability, and hole expansion ratio. The thin steel sheet includes, in weight %, C: 0.02-0.20%, Si: 1.5% or less, Mn: 1.5-3.0%, P: 0.001-0.10%, S: 0.010% or less, SoLAl: 0.01-0.40%, N: 0.020% or less, Cr: 0.3-1.5%, B: 0.0010-0.0060%, Sb: 0.001-0.10%, and including at least one material selected from the group consisting of Ti: 0.003-0.08%, Nb: 0.003-0.08%, and Mo: 0.003-0.08%, and includes Fe and other inevitable impurities as a remainder. Here, Si, Mn, B, Sb, P, and S meet conditions of 5<(Si/Mn+150B)/Sb<20 and C+Mn/20+Si/30+2P+4S<0.27. Also, the manufacturing method can secure workability of the thin steel sheet.

Abstract: A steel sheet for forming having low-temperature heat treatment property, in which heat treatment is performed within a range of lower temperature than a conventional steel sheet in the event of hot press forming or post-heat treatment after cold forming, a method of manufacturing the same, and a method of manufacturing parts using the same. The steel sheet has a composition of, by weight, carbon (C): 0.15 to 0.35%, silicon (Si): 0.5% or less, manganese (Mn): 1.5 to 2.2%, phosphorus (P): 0.025% or less, sulfur (S): 0.01% or less, aluminum (Al): 0.01 to 0.05%, nitrogen (N): 50 to 200 ppm, titanium (Ti): 0.005 to 0.05%, tungsten (W): 0.005 to 0.1%, and boron (B): 1 to 50 ppm, wherein Ti/N: less than 3.4, where Ti/N is the atomic ratio of the corresponding elements, Ceq expressed by the following formula ranges from 0.48 to 0.58, and temperature Ar3 ranges from 670° C. to 725° C. Wherein Ceq=C+Si/24+Mn/6+Ni/40+Cr/5+V/14 where C, Si, Mn, Ni, Cr and V indicate the contents (wt %) of the respective elements.

Abstract: Disclosed is a steel sheet that exhibits an ultra-high strength after hot press forming followed by rapid cooling, and an enhanced yield strength after painting. The steel sheet has a composition comprising 0.1% to 0.5% by weight of C, 0.01% to 1.0% by weight of Si, 0.5% to 4.0% by weight of Mn, 0.1% by weight or less of P, 0.03% by weight or less of S, 0.1% by weight of soluble Al, 0.01% to 0.1% by weight of N, 0.3% by weight or less of W, and the balance Fe and other inevitable impurities. Further disclosed are a hot-pressed part made of the steel sheet and a method for manufacturing the hot-pressed part. The hot-pressed part achieves a high increment in yield strength after heat treatment for painting while ensuring an ultra-high tensile strength. Furthermore, the hot-pressed part exhibits superior adhesion to a coating layer, good surface appearance and improved corrosion resistance after painting.

Abstract: A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Abstract: A repair circuit substitutes a defective cell with a redundancy cell. For the purpose, the repair circuit includes an antifuse programmed by a voltage difference of both ends thereof, a programming circuit for programming the antifuse, a detection circuit for detecting whether the antifuse is programmed or unprogrammed by using a first and a second power stabilization signal of a power up reset circuit, wherein the detection is performed during a power stabilization period or after the power stabilization period, a latch circuit for latching the result of the detection to thereby generate an output signal, and a redundancy circuit having a redundancy cell for repairing the defective cell in response to the output signal of the latch circuit.

Abstract: A semiconductor memory test circuit and a method for the same to reduce the test time in testing a semiconductor memory.

Abstract: An antifuse repair circuit is disclosed for selectively programming a specific antifuse to replace a defective cell with a redundant cell.

Abstract: An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation.

Abstract: A repair circuit substitutes a defective cell with a redundancy cell. For the purpose, the repair circuit includes an antifuse programmed by a voltage difference of both ends thereof, a programming circuit for programming the antifuse, a detection circuit for detecting whether the antifuse is programmed or unprogrammed by using a first and a second power stabilization signal of a power up reset circuit, wherein the detection is performed during a power stabilization period or after the power stabilization period, a latch circuit for latching the result of the detection to thereby generate an output signal, and a redundancy circuit having a redundancy cell for repairing the defective cell in response to the output signal of the latch circuit.

Abstract: An antifuse circuit provides a stabilized high voltage to an antifuse programming circuit through the use of an NC pin which is not used in the chip operation.

Abstract: A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Abstract: An antifuse repair circuit is disclosed for selectively programming a specific antifuse to replace a defective cell with a redundant cell.

Abstract: The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a charge pump; and an anti-fuse unit circuits for the program/read of anti-fuse states. For an anti-fuse program at the special test mode, a program address generation circuit having inputs of control signals and addresses activates the programming voltage generator and makes a special or program address for selection of anti-fuse. In the normal mode, the program address generation circuit and an internal power generator remain at an inactive state. In anti-fuse unit circuit, the program address and the programming voltage signal from the programming voltage generator serve to switch the terminal of the anti-fuse up to a programming voltage level when the anti-fuse is selected for programming of anti-fuse elements.

Abstract: A self-refresh apparatus for a semiconductor memory device is disclosed. According to the self-refresh apparatus, Data loss can be prevented by monitoring a leakage of memory cell data, activating a variable self-refresh signal in accordance with a signal resulted from the monitoring during a self-refresh mode, producing a refresh request signal when the self-refresh signal is activated and then refreshing all of memory cells. An unnecessary power consumption can be also prevented by variably performing the refresh operation in accordance with the retention time of cell data.

Abstract: An internal voltage generating circuit and method for generating thereof in semiconductor device capable of performing test without any needless transfer between a test equipment and a repair equipment are disclosed. The circuit includes a plurality of test power voltage pads, each of which can be selectively applied with the external power voltage and a ground voltage during test; a fuse programmable control signal generator coupled to the plurality of test power voltage pads for generating a control signal according to the signals applied to the plurality of the test power voltage pads during test, and for generating the control signal according to fuse-programmed state after at least one fuse included therein is programmed; a reference voltage generator for receiving the external power voltage so as to produce a reference voltage having a predetermined level; and a voltage trimming unit for trimming the reference voltage in accordance with the output of the fuse programmable control signal generator.

Abstract: A digital audio disc player, having a music memory function which is operative during an intro-play mode of operation, includes a memory for storing at least one of a plurality of music item numbers and an operating sequence for reproduction, an input device for generating an intro key signal initiating a intro-play function, a play key signal causing reproduction of music, and a memory key signal directing storage of a respective music item number during the intro-play operation, a microprocessor performing the intro-play function in response to the intro key signal according to the operating sequence, stores the respective music item number of the currently reproduced music in the memory when the memory key signal key is input during the intro-play operation, and controls reproduction of the music corresponding to the respective music item numbers stored in the memory when the play key signal is input, and a disc reproduction device which demodulates and reproduces a signal recorded on a digital audio disc