Patents by Inventor Jin-Taek Park
Jin-Taek Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210134823Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.Type: ApplicationFiled: June 30, 2020Publication date: May 6, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Min Sung KO, Gwang Been KIM, Hwal Pyo KIM, Jin Taek PARK, Young Ock HONG
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Publication number: 20210091109Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.Type: ApplicationFiled: May 11, 2020Publication date: March 25, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Sae Jun KWON, Seung Min LEE, Hwal Pyo KIM, Jin Taek PARK, Seung Woo HAN, Young Ock HONG
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Publication number: 20210057431Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.Type: ApplicationFiled: April 16, 2020Publication date: February 25, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Sae Jun KWON, Hwal Pyo KIM, Jin Taek PARK, Yang Seok LIM, Young Ock HONG
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Patent number: 10854623Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: GrantFiled: July 12, 2019Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
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Publication number: 20190341396Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: ApplicationFiled: July 12, 2019Publication date: November 7, 2019Inventors: Jang Hyun YOU, Jin Taek PARK, Taek Soo SHIN, Sung Yun LEE
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Patent number: 10355010Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: GrantFiled: October 17, 2016Date of Patent: July 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
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Patent number: 10263009Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width.Type: GrantFiled: October 2, 2017Date of Patent: April 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-hyun Lee, Jin-taek Park, Young-woo Park
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Patent number: 10115799Abstract: There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.Type: GrantFiled: January 17, 2017Date of Patent: October 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Taek Park, Young Woo Park, Jae Duk Lee
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Patent number: 9899412Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.Type: GrantFiled: March 21, 2017Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-goo Lee, Young-woo Park, Jin-taek Park
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Publication number: 20180026050Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width.Type: ApplicationFiled: October 2, 2017Publication date: January 25, 2018Inventors: Chang-hyun LEE, Jin-taek PARK, Young-woo PARK
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Publication number: 20170207232Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.Type: ApplicationFiled: October 17, 2016Publication date: July 20, 2017Inventors: Jang Hyun YOU, Jin Taek PARK, Taek Soo SHIN, Sung Yun LEE
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Publication number: 20170194347Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.Type: ApplicationFiled: March 21, 2017Publication date: July 6, 2017Inventors: Jae-goo Lee, Young-woo Park, Jin-taek Park
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Publication number: 20170125540Abstract: There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.Type: ApplicationFiled: January 17, 2017Publication date: May 4, 2017Inventors: Jin Taek Park, Young Woo Park, Jae Duk Lee
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Patent number: 9620511Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.Type: GrantFiled: May 2, 2014Date of Patent: April 11, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-goo Lee, Young-woo Park, Jin-taek Park
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Patent number: 9564519Abstract: There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.Type: GrantFiled: August 12, 2014Date of Patent: February 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Taek Park, Young Woo Park, Jae Duk Lee
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Patent number: 9343452Abstract: A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.Type: GrantFiled: November 17, 2014Date of Patent: May 17, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Hwan Yun, Jin-Taek Park
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Patent number: 9318329Abstract: Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.Type: GrantFiled: May 7, 2014Date of Patent: April 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kanamori Kohji, Young-Woo Park, Jin-Taek Park, Jae-Duk Lee
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Patent number: 9305830Abstract: A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n?1 first recesses penetrating 20 through 2n?1 deposited sacrificial layers and forming a buried insulating layer group including 2n?1 buried insulating layers filling the 2n?1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n?1 buried insulating layers may be formed.Type: GrantFiled: November 7, 2014Date of Patent: April 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yong Park, Woon-kyung Lee, Jin-taek Park
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Publication number: 20150287710Abstract: A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.Type: ApplicationFiled: November 17, 2014Publication date: October 8, 2015Inventors: Tae-Hwan Yun, Jin-Taek Park
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Patent number: 9082655Abstract: A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region.Type: GrantFiled: February 14, 2014Date of Patent: July 14, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-sun Youm, Sang-young Park, Jin-taek Park, Yong-top Kim