Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where each of the at least one memory transistor is directly connected to at least one of the plurality of bit-line pillars, where the plurality of memory cells include a partially or fully metalized source structure and/or a partially or fully metalized drain structure, where the metalized source includes two metal structures, and where the two metal structures include a tungsten structure.

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least four electronic circuit units (ECUs), where each of the ECUs include a first circuit, the first circuit including a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where each of the at least one memory transistor is directly connected to at least one of the plurality of bit-line pillars, where the plurality of memory cells include a partially or fully metalized source structure and/or a partially or fully metalized drain structure, where the metalized source includes two metal structures, and where the two metal structures include a tungsten structure.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Abstract: The present disclosure relates to a transparent substrate including a multilayer thin film coating, the multilayer thin film coating includes a first dielectric layer, a second dielectric layer, and a metal layer, the metal layer is interposed between the first dielectric layer and the second dielectric layer in direct contact with each of the first dielectric layer and the second dielectric layer, the first dielectric layer includes silicon nitride represented by a chemical formula of Si3N4, the second dielectric layer includes silicon nitride represented by a chemical formula of SiNx (x<1.33), and the metal layer includes one or more selected from the group consisting of Ag, Au, Cu, Al, Pt, Pd, Ni, Co, Fe, Mn, Cr, Mo, W, V, Ta, Nb, Sn, Pb, Sb, and Bi.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the plurality of first memory arrays includes a plurality of first DRAM (Dynamic Random Access Memory) cells, and where the plurality of second memory arrays includes a plurality of second DRAM (Dynamic Random Access Memory) cells.

Abstract: Provided is a transparent substrate with a multilayer thin film coating. The multilayer thin film coating includes a lower dielectric layer, a lower protective layer, a metal functional layer having an infrared reflection function, an upper protective layer, and an upper dielectric layer, which are sequentially laminated from the transparent substrate, the lower dielectric layer includes at least one barrier layer and at least one impurity collection layer, and the thickness of the metal function layer is 12 nm or more.

Abstract: Provided is a transparent substrate with a multilayer thin film coating, in which the multilayer thin film coating includes a lower dielectric layer, a lower protective layer, a metal functional layer having an infrared reflection function, an upper protective layer, and an upper dielectric layer, which are sequentially laminated on the transparent substrate, the thickness of the metal function layer is 12 nm or more, and the thickness of the lower protective layer is larger than that of the upper protective layer and the thickness of the lower protective layer is 2 nm or more.

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least eight ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Abstract: A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least eight ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the plurality of first memory arrays includes a plurality of first DRAM (Dynamic Random Access Memory) cells, and where the plurality of second memory arrays includes a plurality of second DRAM (Dynamic Random Access Memory) cells.

Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where a plurality of the channels are connected to a body pillar, and where the body pillar is at least temporary connected to a negative bias.