Abstract: A black enamel composition includes a glass frit, a black pigment and an organic vehicle, wherein the glass frit includes 50 to 70 wt % of Bi2O3, 7.0 to 10.0 wt % of SiO2, 6.0 to 8.0 wt % of B2O3, 10.0 to 15.0 wt % of ZnO, 1.0 to 2.0 wt % of Al2O3, 3.2 to 10.9 wt % of the total of Co3O4, NiO2 and Fe2O3, based on the total weight of the glass frit, wherein the black pigment is 3 to 10 wt % relative to the total weight of the glass frit.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Abstract: A 3D device, the device including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, and where the third level includes Radio Frequency (“RF”) circuits to drive the special connectivity structures, where the second level overlays the first level, where the third level overlays the second level, and where the fourth level overlays the third level.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A 3D device comprising: a first level comprising first transistors, said first level comprising a first interconnect; a second level comprising second transistors, said second level overlaying said first level; a third level comprising third transistors, said third level overlaying said second level; a plurality of electronic circuit units (ECUs), wherein each of said plurality of ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors, wherein each of said plurality of ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors, wherein each of said plurality of ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors, wherein each of said ECUs comprises a vertical bus, wherein said vertical bus comprises greater than eight pillars and less than three hundred pillars and provides electrical connections between said first circuit and said second circuit.

Abstract: A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

Abstract: A 3D memory device, the device comprising: a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of bit-line pillars, wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain, wherein said bit-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device.

Abstract: An all-printed physically unclonable function based on a single-walled carbon nanotube network. The network may be a mixture of semiconducting and metallic nanotubes randomly tangled with each other through the printing process. The unique distribution of carbon nanotubes in a network can be used for authentication, and this feature can be a secret key for a high level hardware security. The carbon nanotube network does not require any advanced purification process, alignment of nanotubes, high-resolution lithography and patterning. Rather, the intrinsic randomness of carbon nanotubes is leveraged to provide the unclonable aspect.

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Abstract: A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A transparent substrate provided with a multi-layered coating is provided, the coating including the following in an order from the substrate: a first dielectric film including one or more dielectric layers, a first metallic protective layer, a first metallic layer having an infrared (IR) reflection characteristic, a second metallic protective layer, a second dielectric film including two or more dielectric layers, a third metallic protective layer, a second metallic layer having an infrared (IR) reflection characteristic, a fourth metallic protective layer, and a third dielectric film D3 including one or more dielectric layers, wherein the dielectric layer includes a metal oxide, a metal nitride, or a metal oxynitride, the metallic layer is silver (Ag) or a silver (Ag)-containing metal alloy, a normal emissivity is 2.0% or less, and a difference between a coated surface reflectance and an uncoated surface reflectance is 21% or more.

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

Abstract: A glass frit for forming a black enamel coating includes Si at 6.5 mol % to 6.9 mol %, B at 9.0 mol % to 9.3 mol %, Bi at 13.0 mol % to 13.4 mol %, Zn at 6.0 mol % to 6.3 mol %, and Al at 1.5 mol % to 2.0 mol %, and Co, Ni, and Fe, wherein a total amount of Co, Ni, and Fe is 2.9 mol % to 3.5 mol % of the glass frit in a molar ratio.

Abstract: A 3D memory device, the device comprising: a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of bit-line pillars, wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain, wherein said bit-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device.

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.