Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: An aspect of the disclosure provides a signal processing circuit that decouples a timing loop and an equalizer adaptation loop. The signal processing circuit includes an analog to digital converter (ADC), an equalizer, a detector, and a timing module. The ADC is configured to receive an analog signal, sample the analog signal based on a sampling clock signal, and convert the sampled analog signal into a digital signal. The equalizer is configured to equalize the digital signal. The detector is configured to detect a bit stream from the equalized digital signal. The timing module is configured to detect a timing error based on the digital signal before being equalized, and to adjust the sampling clock signal based on the timing error.

Abstract: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

Abstract: Aspects of the disclosure provide a method for signal processing. The method includes receiving a tracking signal corresponding to a recording track on a storage medium. The tracking signal is frequency modulated with encoded symbols. Further, the method includes phase-locking an internal signal to the tracking signal to cause a frequency of the internal signal to be locked at a center frequency of the tracking signal, detecting a drift between the internal signal and the encoded symbols, and phase-shifting the internal signal to compensate for the drift.

Abstract: A system with a nonlinear element processes a replay signal with a scaling factor into a signal compensated for asymmetry. The replay signal may include data from an optical disk. The scaling factor may be estimated based on the compensated signal and a scaling factor gain. The replay signal and the compensated signal may be converted into digital signals and processed digitally. In one embodiment, the compensated signal may be calculated as approximately the scaling factor multiplied by a square of an amplitude of the replay signal added to the amplitude of the replay signal. In another embodiment, the compensated signal may be calculated as approximately the scaling factor multiplied by an absolute value of an amplitude of the replay signal added to the amplitude of the replay signal. A related method is also disclosed. Other embodiments are provided, and each of the embodiments described herein can be used alone or in combination with one another.

Abstract: Devices, systems, methods, and other embodiments associated with clocking a radio frequency channel are described. In one embodiment, an apparatus includes a wobble channel logic configured to at least partially decode a digital wobble signal and configured to control a time base generator to generate a clock signal that is synchronized to wobble data. The apparatus further includes scaling logic to scale the clock signal to produce a scaled clock signal, and radio frequency channel logic configured to at least partially decode a digital radio frequency signal. The radio frequency channel logic is configured to be clocked by the clock signal and the wobble channel logic is configured to be clocked by the scaled clock signal.

Abstract: Aspects of the disclosure provide a signal processing circuit to reduce signal distortions due to optical aberrations. The signal processing circuit includes a circuit configured to receive an electrical signal corresponding to a light beam reflected by a storage medium and filter the electrical signal to reduce distortions due to, for example, birefringence aberration in the light beam, and an equalizer configured to equalize the filtered electrical signal. In an example, the circuit is a median filter.

Abstract: A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a second decoding iteration to decode the data. The first decoding iteration includes generating a resultant matrix. The first module is configured to, based on first decoding statuses of multiple bytes in the resultant matrix, determine second decoding statuses of bytes proximate to failed bytes of a feedback matrix. The feedback matrix is generated based on the resultant matrix. The first module is configured to mark selected ones of the failed bytes as erasures based on the second decoding statuses. The second module is configured to correct one or more of the bytes marked as erasures during the second decoding iteration.

Abstract: Described herein are pyrrolo[2,3-d]pyrimidine compounds, their use as Janus Kinase (JAK) inhibitors, pharmaceutical compositions containing these compounds, and methods for their preparation.

Abstract: A differential phase detector for an optical storage system is set forth. The differential phase detector includes a photodetector circuit arranged to detect light deviations associated with radial errors in the optical storage system. A non-linear equalizer is in communication with the photodetector circuit. The output of the non-linear equalizer is in communication with signal processing circuitry. The signal processing circuitry uses the equalized signals to generate one or more radial error signals.

Abstract: New and useful methods and systems for providing improved performance of a Viterbi device are disclosed. For example, in an embodiment a Viterbi device includes metric circuitry configured to determine branch metrics using at least one of a variance signal based on both received data and detected data of the Viterbi device and a priori probabilities of available state transitions within a trellis of the Viterbi device.

Abstract: A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.

Abstract: Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes an analog to digital converter (ADC) configured to receive an analog input signal, sample the analog input signal based on a sampling clock signal, and convert the sampled analog input signal into a digital output signal, an equalizer configured to equalize the digital output signal, a phase-shift module configured to phase-shift the equalized digital output signal based on a phase-shift signal, and a timing compensation module coupled to the phase-shift module to detect a timing error, and to adjust the phase-shift signal based on the timing error.

Abstract: Aspects of the disclosure provide a signal processing circuit that includes a signal processing circuit includes a processing path configured to process an electrical signal to produce input data samples, and a feed-forward correction module configured to delay the input data samples to produce delayed data samples, to apply the delayed data samples to a timing loop during periods when a profile variation of the data samples is not detected, and to apply the input data sample to the timing loop during periods when a profile variation of the data samples is detected.

Abstract: A sync mark detector for detecting a sync mark having alternative polarities includes an input terminal receiving data bits, wherein the data bits include constant bit groups and each constant bit group includes consecutive bits of the same logic value, the first unit outputting constant bit length values that are representative of bit lengths of constant bit groups, respectively, the second unit outputting combined bit length values, wherein each combined bit length value is representative of a sum of two consecutive constant bit length values, the third unit comparing each combined bit length value to a largest previous combined bit length value to determine a largest combined bit length value, the fourth unit determining a threshold value based on the largest combined bit length value, and the fifth unit outputting a sync mark detection signal when an individual combined bit length value is larger than the threshold value.

Abstract: Devices, systems, methods, and other embodiments associated with clocking a radio frequency channel are described. In one embodiment, an apparatus includes a wobble channel logic configured to at least partially decode a digital wobble signal and configured to control a time base generator to generate a clock signal that is synchronized to wobble data. The apparatus further includes downsampling logic to scale the clock signal to produce a scaled clock signal, and a radio frequency channel logic to at least partially decode a digital radio frequency signal. The clocking signal is connected to clock the radio frequency channel logic, and the scaled clocking signal is connected to clock the wobble channel logic.

Abstract: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

Abstract: A differential phase detector for an optical storage system is set forth. The differential phase detector includes a photodetector circuit arranged to detect light deviations associated with radial errors in the optical storage system. A non-linear equalizer is in communication with the photodetector circuit. The output of the non-linear equalizer is in communication with signal processing circuitry. The signal processing circuitry uses the equalized signals to generate one or more radial error signals.

Abstract: A phase detector comprises a first slicing circuit that generates a first digital signal corresponding to a logic state of a first generally continuous signal. A second slicing circuit generates a second digital signal corresponding to a logical state of a second generally continuous signal. Phase detector logic compares triggering edges of the first and second digital signals to generate a phase difference signal having a pulse width corresponding to a phase difference between the first and second generally continuous signals. Aberration compensation circuitry is in communication with the phase detector logic to ensure generation of the phase difference signal in the presence of signal aberrations occurring at the triggering edges of the first and second digital signals.

Abstract: Described herein are pyrrolo[2,3-d]pyrimidine compounds, their use as Janus Kinase (JAK) inhibitors, pharmaceutical compositions containing these compounds, and methods for their preparation.