Patents by Inventor Jing-Hong Conan Zhan
Jing-Hong Conan Zhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8941448Abstract: An M-way coupler having a first port, M second ports, M transmission line sections, M isolation resistors and a phase shifting network is disclosed, where M is an integer number greater than 1. The M transmission line sections couple the first port to the M second ports, respectively. Each of the M isolation resistors has a first terminal and a second terminal. The first terminals of the M isolation resistors are coupled to the M second ports, respectively. The phase shifting network has M I/O terminals coupled to the second terminals of the M isolation resistors, respectively. The phase shifting network is arranged to provide a phase shift within a predetermined tolerance margin between arbitrary two I/O terminals of the M I/O terminals of the phase shifting network.Type: GrantFiled: October 13, 2011Date of Patent: January 27, 2015Assignee: Mediatek Singapore Pte. Ltd.Inventors: Tiku Yu, Jing-Hong Conan Zhan
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Patent number: 8878582Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.Type: GrantFiled: September 12, 2012Date of Patent: November 4, 2014Assignee: Mediatek Inc.Inventors: Yu-Li Hsueh, Chih-Hsien Shen, Jing-Hong Conan Zhan
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Patent number: 8791732Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.Type: GrantFiled: November 8, 2011Date of Patent: July 29, 2014Assignee: MediaTek Inc.Inventors: Jui-Lin Hsu, Chih-Hsien Shen, Chunwei Chang, Jing-Hong Conan Zhan
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Publication number: 20140203853Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.Type: ApplicationFiled: January 17, 2014Publication date: July 24, 2014Applicant: Mediatek Inc.Inventors: Yu-Li HSUEH, Jing-Hong Conan ZHAN
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Patent number: 8766684Abstract: A phase/frequency detector for controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.Type: GrantFiled: February 18, 2013Date of Patent: July 1, 2014Assignee: Mediatek Inc.Inventors: Yu-Li Hsueh, Yi-Hsien Cho, Jing-Hong Conan Zhan
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Patent number: 8664985Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.Type: GrantFiled: July 12, 2012Date of Patent: March 4, 2014Assignee: Mediatek Inc.Inventors: Yu-Li Hsueh, Jing-Hong Conan Zhan
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Patent number: 8653564Abstract: A millimeter-wave transistor device includes a plurality of sub-cells arranged in matrix array, each of the sub-cells having a longitudinal gate finger elongating along a reference y-axis, a source doping region disposed at one side of the longitudinal gate finger and a drain doping region at the other side of the longitudinal gate finger opposite to the source doping region; and at least three parallel connecting bars extending along a reference x-axis, electrically connecting with respective distal ends of the longitudinal gate finger of each of the sub-cells.Type: GrantFiled: September 1, 2009Date of Patent: February 18, 2014Assignee: Mediatek Inc.Inventor: Jing-Hong Conan Zhan
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Publication number: 20130200922Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.Type: ApplicationFiled: July 12, 2012Publication date: August 8, 2013Applicant: MEDIATEK INC.Inventors: Yu-Li HSUEH, Jing-Hong Conan ZHAN
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Publication number: 20130156085Abstract: The calibration method, performed on a phased array device including channel elements coupled in parallel by a transmission line, has the steps of: obtaining channel responses corresponding to the channel elements through the transmission line, and each of the channel responses is obtained when one of the channel elements is turned on, and the rest of the channel elements are turned off; calculating a characteristic value corresponding to the transmission line based on the obtained channel responses of the channel elements; and adjusting a channel parameter of one of the channel elements based on the characteristic value of the transmission line.Type: ApplicationFiled: September 12, 2012Publication date: June 20, 2013Applicant: MEDIATEK SINGAPORE PTE. LTD.Inventors: Sean Timothy NICOLSON, ChuanKang LIANG, Jing-Hong Conan ZHAN
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Publication number: 20130141149Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.Type: ApplicationFiled: September 12, 2012Publication date: June 6, 2013Applicant: MEDIATEK INC.Inventors: Yu-Li HSUEH, Chih-Hsien SHEN, Jing-Hong Conan ZHAN
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Patent number: 8429487Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.Type: GrantFiled: December 31, 2010Date of Patent: April 23, 2013Assignee: Mediatek Inc.Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
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Publication number: 20130093533Abstract: An M-way coupler having a first port, M second ports, M transmission line sections, M isolation resistors and a phase shifting network is disclosed, where M is an integer number greater than 1. The M transmission line sections couple the first port to the M second ports, respectively. Each of the M isolation resistors has a first terminal and a second terminal. The first terminals of the M isolation resistors are coupled to the M second ports, respectively. The phase shifting network has M I/O terminals coupled to the second terminals of the M isolation resistors, respectively. The phase shifting network is arranged to provide a phase shift within a predetermined tolerance margin between arbitrary two I/O terminals of the M I/O terminals of the phase shifting network.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: MEDIATEK SINGAPORE PTE. LTD.Inventors: Tiku Yu, Jing-Hong Conan Zhan
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Patent number: 8400199Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.Type: GrantFiled: April 28, 2011Date of Patent: March 19, 2013Assignee: Mediatek Inc.Inventors: Yu-Li Hsueh, Yi-Hsien Cho, Jing-Hong Conan Zhan
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Patent number: 8395453Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.Type: GrantFiled: September 23, 2008Date of Patent: March 12, 2013Assignee: Mediatek Inc.Inventors: Hsiang-Hui Chang, Bing-Yu Hsieh, Jing-Hong Conan Zhan
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Publication number: 20130005275Abstract: The transceiver has a transmitter, a receiver, and a three-port network. The transmitter is configured to transmit an outgoing RF signal. The receiver is configured to receive an incoming RF signal. The three-port network includes: a transmission line, configured to have a line length less than a quarter of a wavelength of the incoming RF signal; an antenna port, configured to connect to an antenna; a receiver port, configured to connect the receiver to the antenna port; and a transmitter port, configured to connect the transmitter to the antenna port and the receiver port through the transmission line.Type: ApplicationFiled: November 21, 2011Publication date: January 3, 2013Applicant: MEDIATEK INC.Inventors: Sean Timothy Nicolson, Jing-Hong Conan Zhan
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Patent number: 8319532Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.Type: GrantFiled: April 28, 2011Date of Patent: November 27, 2012Assignee: Mediatek Inc.Inventors: Yu-Li Hsueh, Jing-Hong Conan Zhan
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Publication number: 20120293362Abstract: A phase-arrayed device includes: a signal processing circuit arranged to generate a specific signal; a first phase-arrayed channel arranged to provide a first phase-arrayed signal according to the specific signal; a first conducting path arranged to conduct the specific signal to the first phase-arrayed channel; a second conducting path arranged to conduct the first phase-arrayed signal to the signal processing circuit; and a detecting circuit, arranged to detect a mismatch between the first phase-arrayed signal and a reference signal to generate a detecting signal utilized for calibrating the first phase-arrayed signal.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Inventors: Chuan-Kang Liang, Jing-Hong Conan Zhan, Ti-Ku Yu, Zhiming Deng
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Publication number: 20120294338Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas, at least one of the transceiving elements comprising a first transmitting circuit and a first receiving circuit; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first path from the antenna through the first receiving circuit to the signal processing block and a second path from the signal processing block through the first transmitting circuit to the antenna share at least partial signal traces of the phased-array transceiver.Type: ApplicationFiled: November 22, 2011Publication date: November 22, 2012Inventors: Jing-Hong Conan Zhan, Chuan-Kang Liang, Ti-Ku Yu, Zhiming Deng
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Publication number: 20120286391Abstract: A semiconductor circuit is provided. The semiconductor circuit includes a metal layer, a conductive layer disposed under the metal layer and a semiconductor device disposed under the conductive layer. The metal layer forms an inductor device. The semiconductor device is coupled to the inductor device.Type: ApplicationFiled: November 8, 2011Publication date: November 15, 2012Applicant: MediaTek Inc.Inventors: Chih-Hsien Shen, Jui-Lin Hsu, Chunwei Chang, Jing-Hong Conan Zhan
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Publication number: 20120286834Abstract: A phase locked loop is provided. The phase locked loop includes a detector, a controlled oscillator and a filtering unit coupled between the detector and the controlled oscillator. The detector generates a phase difference signal according to a reference frequency and an oscillation signal. The controlled oscillator generates the oscillation signal according to a filtered signal. The filtering unit filters the phase difference signal to generate the filtered signal, and the filtering unit has a high frequency filter of which a pole is greater than the reference frequency and less than a frequency of the oscillation signal.Type: ApplicationFiled: November 8, 2011Publication date: November 15, 2012Applicant: MEDIATEK INC.Inventors: Jui-Lin Hsu, Chih-Hsien Shen, Chunwei Chang, Jing-Hong Conan Zhan