Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.

Abstract: A phase shifter and related load device are provided. The phase shifter includes a phase shifter core and load devices. The phase shifter core has an input port for receiving an input signal, an output port for outputting an output signal, and connection ports. The load devices are coupled to the connection ports, respectively. At least one of the load devices includes first varactor units each having a first node and a second node, where first nodes of the first varactor units are coupled to a first voltage, second nodes of the first varactor units are respectively coupled to a plurality of second voltages, and the second voltages include at least two voltages different from each other. The phase shifter and related load device are capable of mitigating effects resulted from varactor's non-linear C-V curve.

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.

Abstract: A load device has tunable capacitive units including at least a first tunable capacitive unit and a second tunable capacitive unit with different inherent capacitive characteristics, respectively. Each of the first tunable capacitive unit and the second tunable capacitive unit has a first node and a second node, where the first nodes of the first tunable capacitive unit and the second tunable capacitive unit are coupled to a first voltage, the second node of the first tunable capacitive unit is coupled to a second voltage, and the second node of the second tunable capacitive unit is coupled to a third voltage.

Abstract: An embodiment of the voltage controlled oscillator is provided. The oscillator comprises a first inductor set, a second inductor set, a second capacitor, a voltage source and a negative resistance element. The inductance of the second inductor set is k times the inductance of the first inductor set. The voltage source applies an ac voltage to the second inductor set. The negative resistance element is coupled to the second inductor set to provide a negative resistance to resonate the second capacitor at the second inductor set.

Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.

Abstract: An amplifier amplifying an input signal and the method thereof. The amplifier comprises first and second transconductor circuits. The first transconductor circuit, coupled to the first transistor, receives the first noise voltage to generate a first noise current. The second transconductor circuit, coupled in parallel to the first transconductor circuit, receives the second noise voltage to generate a second noise current such that the first and second noise currents cancel each other out to reduce a noise component in the output current when summing up together, and the first and second transconductor circuits are operated in a current mode.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

Abstract: An amplifier amplifying an input signal and the method thereof. The amplifier comprises first and second transconductor circuits. The first transconductor circuit, coupled to the first transistor, receives the first noise voltage to generate a first noise current. The second transconductor circuit, coupled in parallel to the first transconductor circuit, receives the second noise voltage to generate a second noise current such that the first and second noise currents cancel each other out to reduce a noise component in the output current when summing up together, and the first and second transconductor circuits are operated in a current mode.

Abstract: An amplifier amplifying an input signal and the method thereof. The amplifier comprises an impedance matching network and a transconductor amplifier. The impedance matching network receives the input signal to perform impedance matching thereon, and comprises a first resistor, a first transistor, and a second resistor. The first resistor, receives the input signal to generate a matched signal. The first transistor coupled to the first resistor, has a channel thermal noise to establish a first noise voltage. The second resistor coupled to the first resistor and transistor, receives the channel thermal noise to establish a second noise voltage. The transconductor amplifier coupled to the impedance matching network, comprises first and second transconductor circuits. The first transconductor circuit with first transconductance, coupled to the first resistor and transistor, receives the first noise voltage to generate a first noise current.

Abstract: An embodiment of the voltage controlled oscillator is provided. The oscillator comprises a first inductor set, a second inductor set, a second capacitor, a voltage source and a negative resistance element. The inductance of the second inductor set is k times the inductance of the first inductor set. The voltage source applies an ac voltage to the second inductor set. The negative resistance element is coupled to the second inductor set to provide a negative resistance to resonate the second capacitor at the second inductor set.

Abstract: An amplifier amplifying an input signal and the method thereof. The amplifier comprises an impedance matching network and a transconductor amplifier. The impedance matching network receives the input signal to perform impedance matching thereon, and comprises a first resistor, a first transistor, and a second resistor. The first resistor, receives the input signal to generate a matched signal. The first transistor coupled to the first resistor, has a channel thermal noise to establish a first noise voltage. The second resistor coupled to the first resistor and transistor, receives the channel thermal noise to establish a second noise voltage. The transconductor amplifier coupled to the impedance matching network, comprises first and second transconductor circuits. The first transconductor circuit with first transconductance, coupled to the first resistor and transistor, receives the first noise voltage to generate a first noise current.

Abstract: A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error o a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.