Patents by Inventor Jing-Horng Gau

Jing-Horng Gau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7157766
    Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: January 2, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Jing-Horng Gau, Anchor Chen
  • Patent number: 7071070
    Abstract: A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: July 4, 2006
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Patent number: 7042326
    Abstract: A symmetrical inductor includes a first metal layer, the first metal layer having a first conductive segment disposed on a first side of a line, and a second conductive segment disposed on a second side of the line, the second conductive segment and the first conductive segment being symmetrical to the line; a second metal layer, the second metal layer having a third conductive segment disposed on the first side of the line, and a fourth conductive segment disposed on the second side of the line, the fourth conductive segment and the third conductive segment being symmetrical to the line; a first contact plug for connecting the first conductive segment with a first end of the third conductive segment; a second contact plug for connecting the first conductive segment with a second end of the third conductive segment; a third contact plug for connecting the second conductive segment with a first end of the fourth conductive segment, the third contact plug and the first contact plug being symmetrical to the line
    Type: Grant
    Filed: January 11, 2004
    Date of Patent: May 9, 2006
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Publication number: 20060068559
    Abstract: A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.
    Type: Application
    Filed: September 24, 2004
    Publication date: March 30, 2006
    Inventor: Jing-Horng Gau
  • Patent number: 6977198
    Abstract: A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: December 20, 2005
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Publication number: 20050266633
    Abstract: A method for fabricating a capacitor is described. A metal layer is formed on a substrate, and then an insulating layer is formed over the substrate covering the metal layer. At least one opening is formed in the insulating layer exposing a portion of the metal layer, and a metal spacer is formed on the sidewall of the opening, wherein the metal spacer and the metal layer together constitute a lower electrode. A dielectric layer is formed on the lower electrode, and then an upper electrode is formed on the dielectric layer.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 1, 2005
    Inventor: Jing-Horng Gau
  • Publication number: 20050224917
    Abstract: A junction diode comprising a first conductive type substrate, a second conductive type embedded region, a second conductive type well, a first conductive type doped region and a second conductive type doped region is provided. The second conductive type embedded region is formed within the first conductive type substrate. The second conductive type well is formed within the second conductive type embedded region. The concentration of dopants in the second conductive type well is smaller than the concentration of dopants in the second conductive type embedded region. The first conductive type doped region is formed in the second conductive type well. The second conductive type doped region is formed in the second conductive type embedded region. The junction diode has a smaller capacitance serves as an electrostatic discharge protection device for a radio frequency (RF) circuit without adversely affecting the transmission rate of the RF circuit.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 13, 2005
    Inventor: Jing-Horng Gau
  • Patent number: 6949438
    Abstract: A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed on the substrate, the protective layer having an opening to expose the doping region. A first doping layer of a second conductive type and a second doping layer of the first conductive type are formed on the doping region, respectively, to complete fabrication of a bipolar junction transistor.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: September 27, 2005
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Patent number: 6949440
    Abstract: A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.
    Type: Grant
    Filed: November 11, 2003
    Date of Patent: September 27, 2005
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Patent number: 6943399
    Abstract: A varactor is provided. The varactor includes a second type substrate, two gate structures, a first type doped region and a second type doped region. The two gate structures are disposed over the substrate, and each of the gate structures includes an inter-gate dielectric layer and a gate conductive layer. The first type doped region is disposed in the substrate between the two gate structures. The second type doped region is disposed in the substrate at a side of the two gate structures apart from the first type doped region. The first type doped region is electrically connected to a first electrode, and second type doped region is electrically connected to a second electrode, and the two gate structures are electrically connected to the first electrode or the second electrode.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: September 13, 2005
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau
  • Publication number: 20050151612
    Abstract: A symmetrical inductor includes a first metal layer, the first metal layer having a first conductive segment disposed on a first side of a line, and a second conductive segment disposed on a second side of the line, the second conductive segment and the first conductive segment being symmetrical to the line; a second metal layer, the second metal layer having a third conductive segment disposed on the first side of the line, and a fourth conductive segment disposed on the second side of the line, the fourth conductive segment and the third conductive segment being symmetrical to the line; a first contact plug for connecting the first conductive segment with a first end of the third conductive segment; a second contact plug for connecting the first conductive segment with a second end of the third conductive segment; a third contact plug for connecting the second conductive segment with a first end of the fourth conductive segment, the third contact plug and the first contact plug being symmetrical to the line
    Type: Application
    Filed: January 11, 2004
    Publication date: July 14, 2005
    Inventor: Jing-Horng Gau
  • Patent number: 6905935
    Abstract: A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: June 14, 2005
    Assignee: United Micrelectronics Corp.
    Inventors: Jing-Horng Gau, Anchor Chen
  • Publication number: 20050118778
    Abstract: A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.
    Type: Application
    Filed: January 6, 2005
    Publication date: June 2, 2005
    Inventor: Jing-Horng Gau
  • Publication number: 20050118772
    Abstract: A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 2, 2005
    Inventors: Jing-Horng Gau, Anchor Chen
  • Publication number: 20050116276
    Abstract: A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.
    Type: Application
    Filed: November 28, 2003
    Publication date: June 2, 2005
    Inventor: Jing-Horng Gau
  • Publication number: 20050112837
    Abstract: A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed on the substrate, the protective layer having an opening to expose the doping region. A first doping layer of a second conductive type and a second doping layer of the first conductive type are formed on the doping region, respectively, to complete fabrication of a bipolar junction transistor.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 26, 2005
    Inventor: Jing-Horng Gau
  • Publication number: 20050101098
    Abstract: A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.
    Type: Application
    Filed: November 11, 2003
    Publication date: May 12, 2005
    Inventor: Jing-Horng Gau
  • Patent number: 6884689
    Abstract: A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: April 26, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Ya Chuang, Jing-Horng Gau, Anchor Chen
  • Patent number: 6882029
    Abstract: A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor.
    Type: Grant
    Filed: November 27, 2003
    Date of Patent: April 19, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Jing-Horng Gau, Anchor Chen
  • Patent number: 6881638
    Abstract: A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed on the substrate, the protective layer having an opening to expose the doping region. A first doping layer of a second conductive type and a second doping layer of the first conductive type are formed on the doping region, respectively, to complete fabrication of a bipolar junction transistor.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: April 19, 2005
    Assignee: United Microelectronics Corp.
    Inventor: Jing-Horng Gau