Abstract: A method of fabricating a capacitor. A crown-shape bottom storage node is formed on a conductive region. The crown-shape bottom storage node has a wavelike interior surface and a hemi-spherical grained exterior surface. A dielectric layer is formed on the bottom storage node, and a top electrode is formed to cover the dielectric layer.

Abstract: A fabrication method for a capacitor is proposed, beginning with a semiconductor substrate having a bit line and a planarized first dielectric layer formed thereon. A first silicon nitride layer is formed on the first dielectric layer, followed by forming in sequence a second dielectric layer and a second silicon nitride layer on the first silicon nitride layer. A photolithography and etching process is performed to form an opening in the second dielectric layer and the second silicon nitride layer. A conducting spacer is formed on a sidewall of the opening. With the spacer serving as a mask, the first silicon nitride layer and the first dielectric layer are etched to form a terminal contact opening. A conducting layer is then formed to cover the second silicon nitride layer and to fill the terminal contact opening, while the conducting layer on the second silicon nitride layer is removed by etching back.

Abstract: A shallow trench isolation process is described. A pad oxide layer is formed over a substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer is patterned. The pad oxide layer and the substrate are etched using the patterned silicon nitride as an etching mask, and thus a trench is formed in the substrate. A liner oxide layer is grown over the trench. An oxide layer is deposited to fill the trench in the substrate and has a surface level higher than the silicon nitride layer. The oxide layer is polished to partially remove the oxide layer over the silicon nitride layer. The silicon nitride layer is removed from the substrate, by which removal the oxide layer has an exposed sidewall. A polysilicon spacer is formed on the exposed sidewall. The pad oxide layer is removed. The polysilicon spacer is oxidized and transformed into an oxide spacer.

Abstract: A method of fabricating a DRAM capacitor. A conductive layer and an amorphous silicon layer are formed on a substrate having a dielectric layer. The amorphous silicon layer and the conductive layer are etched to form a region of a capacitor to expose a portion of the dielectric layer. An opening with a profile having a wider upper portion and a narrower lower portion is formed within the conductive layer, and through the opening, the dielectric layer is then etched through to form a node contact window to expose the substrate. An amorphous silicon spacer is formed on the sidewall of conductive layer of the region of the capacitor and fills the node contact window. A selective HSG-Si, a dielectric layer and a polysilicon layer are formed to achieve the fabrication of the capacitor. The conductive layer, the amorphous silicon layer and the HSG-Si serve as a lower electrode of the capacitor and the polysilicon layer serves as an upper electrode of the capacitor.

Abstract: A method of manufacturing a liner insulating layer for a node contact hole. A substrate having an first insulating layer formed thereon is provided, wherein the first insulating layer has a node contact hole penetrating through the first insulating layer and exposing the substrate. A protective layer is formed on the substrate exposed by the node contact hole. A liner insulating layer is formed on the first insulating layer and in the node contact hole. A second insulating layer is formed on a portion of the liner insulating layer formed on the sidewall of the node contact hole. A portion of the liner insulating layer uncovered by the second insulating layer is removed. The protective layer and the second insulating layer are removed.

Abstract: A method of fabricating bit lines by damascene. A substrate having a first dielectric layer is provided, and a bit line contact is formed within the first dielectric layer. A hard material layer is formed on the first dielectric layer to expose the bit line contact. A second dielectric layer is formed on the hard material layer. An opening and a trench are formed within the second dielectric layer to expose the bit line contact and the hard material layer. A hard material spacer is formed on the sidewall of the opening and the trench. A tungsten silicide layer fills the opening and the trench to serve as a bit line on the bit line contact and an interconnect of the bit line.

Abstract: A self-aligned contact process for fabricating semiconductor devices on a semiconductor substrate is described. The present process comprises providing two gates structure on a semiconductor substrate, wherein the gate structure comprises a gate and a passivation layer on the top surface thereof. A buffer layer is conformally overlaid on the gate structure, passivation layer and the semiconductor substrate. A photoresist material is formed on the semiconductor substrate to a level between the top surface of the passivation layer and interface between the passivation layer and gate. The buffer layer is removed to the level of the photoresist layer. Next, the photoresist material is removed. A spacer is formed on the sidewall of the buffer layer and the passivation layer of the gate structure. An insulating layer is formed on the semiconductor substrate and then, a contact opening is formed therein to expose the semiconductor substrate.

Abstract: A method is described for manufacturing shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer, a trench penetrating through the mask layer and the pad oxide and into the substrate and a first liner oxide layer in the trench. A portion of the first liner oxide layer is stripped away to expose the bottom corner of the mask layer. A portion of the mask layer is stripped away to expose the top corner of the first oxide layer. The first liner oxide layer is removed to expose the surface of the trench. A second liner oxide layer is formed on the sidewall and the base surface of the trench and the trench is filled with an insulating material to form a shallow trench isolation.