Patents by Inventor Jingcheng Zhuang
Jingcheng Zhuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11264995Abstract: A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signaType: GrantFiled: October 26, 2020Date of Patent: March 1, 2022Assignee: QUALCOMM IncorporatedInventors: Yue Chao, Yiwu Tang, Yunliang Zhu, Dongmin Park, Jingcheng Zhuang
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Patent number: 10575279Abstract: An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.Type: GrantFiled: April 1, 2016Date of Patent: February 25, 2020Assignee: QUALCOMM IncorporatedInventors: Bhushan Shanti Asuri, Jingcheng Zhuang, Praveen Sampath, Shrenik Patel, Jeremy Darren Dunworth, Lai Kan Leung, Gurkanwal Singh Sahota, Jong Min Park
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Patent number: 10534025Abstract: A phase frequency detector (PFD) isolates supply (e.g., voltage supply) to a reference path and a feedback path of a phase locked loop (PLL) such that the power supply to the reference path is independent of the power supply to the feedback path. This isolation improves linearity. In one instance, the PFD includes a supply voltage, one or more switches, a reference capacitor and a feedback capacitor. The reference capacitor is selectively coupled to the supply voltage via the one or more switches and the feedback capacitor is selectively coupled to the supply voltage via the one or more switches.Type: GrantFiled: September 20, 2017Date of Patent: January 14, 2020Assignee: QUALCOMM IncorporatedInventor: Jingcheng Zhuang
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Patent number: 10523272Abstract: An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.Type: GrantFiled: May 26, 2017Date of Patent: December 31, 2019Assignee: QUALCOMM IncorporatedInventors: Madhukar Vallabhaneni, Girish Koppassery, Xinhua Chen, Jingcheng Zhuang
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Patent number: 10256796Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.Type: GrantFiled: March 3, 2017Date of Patent: April 9, 2019Assignee: QUALCOMM IncorporatedInventors: Shih-Chieh Hsin, Med Nariman, Jingcheng Zhuang
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Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation
Patent number: 10177772Abstract: A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.Type: GrantFiled: September 21, 2016Date of Patent: January 8, 2019Assignee: QUALCOMM IncorporatedInventors: Jingcheng Zhuang, Xinhua Chen, Frederic Bossu, Yiwu Tang -
Publication number: 20180356451Abstract: A phase frequency detector (PFD) isolates supply (e.g., voltage supply) to a reference path and a feedback path of a phase locked loop (PLL) such that the power supply to the reference path is independent of the power supply to the feedback path. This isolation improves linearity. In one instance, the PFD includes a supply voltage, one or more switches, a reference capacitor and a feedback capacitor. The reference capacitor is selectively coupled to the supply voltage via the one or more switches and the feedback capacitor is selectively coupled to the supply voltage via the one or more switches.Type: ApplicationFiled: September 20, 2017Publication date: December 13, 2018Inventor: Jingcheng ZHUANG
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Publication number: 20180343032Abstract: An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Inventors: Madhukar Vallabhaneni, Girish Koppassery, Xinhua Chen, Jingcheng Zhuang
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Patent number: 10116315Abstract: A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.Type: GrantFiled: September 21, 2017Date of Patent: October 30, 2018Assignee: QUALCOMM IncorporatedInventors: Jingcheng Zhuang, Frederic Bossu
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Publication number: 20180254772Abstract: A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.Type: ApplicationFiled: March 3, 2017Publication date: September 6, 2018Inventors: Shih-Chieh Hsin, Med Nariman, Jingcheng Zhuang
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Patent number: 9998129Abstract: A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.Type: GrantFiled: September 21, 2017Date of Patent: June 12, 2018Assignee: QUALCOMM IncorporatedInventors: Jingcheng Zhuang, Jianyun Hu, Animesh Paul, Xinhua Chen, Frederic Bossu
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Patent number: 9973182Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.Type: GrantFiled: September 14, 2016Date of Patent: May 15, 2018Assignee: QUALCOMM IncorporatedInventors: Animesh Paul, Jingcheng Zhuang, Xinhua Chen, Ravi Sridhara
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Publication number: 20180076805Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.Type: ApplicationFiled: September 14, 2016Publication date: March 15, 2018Inventors: Animesh PAUL, Jingcheng ZHUANG, Xinhua CHEN, Ravi SRIDHARA
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Patent number: 9893875Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.Type: GrantFiled: September 20, 2016Date of Patent: February 13, 2018Assignee: QUALCOMM IncorporatedInventors: Marco Zanuso, Mohammad Elbadry, Tsai-Pi Hung, Ravi Sridhara, Francesco Gatta, Jingcheng Zhuang
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FRACTIONAL-N PHASE LOCKED LOOP DELTA SIGMA MODULATOR NOISE REDUCTION USING CHARGE PUMP INTERPOLATION
Publication number: 20180019756Abstract: A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.Type: ApplicationFiled: September 21, 2016Publication date: January 18, 2018Inventors: Jingcheng ZHUANG, Xinhua CHEN, Frederic BOSSU, Yiwu TANG -
Patent number: 9864341Abstract: An integrated circuit (IC) is disclosed for time-to-digital conversion with a latch-based ring. In example aspects, the IC includes a ring, a counter, an encoder, and time-to-digital converter (TDC) control circuitry. The ring includes multiple ring stages and propagates a ring signal between successive ring stages. Each respective ring stage includes latch circuitry to secure a state of the ring signal at the respective ring stage. The ring provides a ring output signal using the latch circuitry of each of the ring stages. The ring is coupled to the counter. The counter increments a counter value responsive to the ring signal and provides a counter output signal based on the counter value. The encoder is coupled to the ring and the counter. The encoder generates a TDC output signal based on the ring and counter output signals. The TDC control circuitry operates the ring responsive to a TDC input signal.Type: GrantFiled: December 2, 2016Date of Patent: January 9, 2018Assignee: QUALCOMM IncorporatedInventor: Jingcheng Zhuang
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Publication number: 20170338940Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.Type: ApplicationFiled: September 20, 2016Publication date: November 23, 2017Inventors: Marco ZANUSO, Mohammad ELBADRY, Tsai-Pi HUNG, Ravi SRIDHARA, Francesco GATTA, Jingcheng ZHUANG
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Publication number: 20170094641Abstract: An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.Type: ApplicationFiled: April 1, 2016Publication date: March 30, 2017Inventors: Bhushan Shanti Asuri, Jingcheng Zhuang, Praveen Sampath, Shrenik Patel, Jeremy Darren Dunworth, Lai Kan Leung, Gurkanwal Singh Sahota, Jong Min Park
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Patent number: 9584184Abstract: Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.Type: GrantFiled: March 5, 2013Date of Patent: February 28, 2017Assignee: QUALCOMM IncorporatedInventors: Miao Li, Xiaohua Kong, Jingcheng Zhuang, Wei Wang
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Patent number: 9520887Abstract: Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.Type: GrantFiled: March 3, 2016Date of Patent: December 13, 2016Assignee: Qualcomm IncorporatedInventors: Jingcheng Zhuang, Jong Min Park, Lai Kan Leung, Yiwu Tang