Abstract: A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.

Abstract: A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.

Abstract: Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Abstract: Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.

Abstract: A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract: Clock and data recovery (CDR) circuits and resettable voltage controlled oscillators (VCOs) are disclosed. In one embodiment, the CDR circuit includes a sampler configured to receive a data stream in a data path and sample the data stream. However, a clock signal of the data stream needs to be recovered to sample the data stream since the data stream may not be accompanied by the clock signal. To recover the clock signal from the data stream, the CDR circuit may have a resettable VCO configured to generate a clock output. The sampler and the resettable VCO may be operably associated so that the sampler samples the data stream in the data path based on the clock output. The resettable VCO can be reset to adjust a clock phase of the clock output and help reduce sampling errors resulting from drift of the clock output and/or the data stream.

Abstract: A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.

Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Abstract: Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.

Abstract: A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: Transmission of information between user equipment (UE) and base stations in a wireless network occurs using a stream of periodic data. A modem in the UE operates synchronized to a first clock source to produce the stream of periodic data at a chip rate. Transceiver circuitry is synchronized to a variable clock source to receive the stream of data from the first circuitry at a rate according to the variable clock source. A fixed phase relationship is maintained between the variable clock source and the first clock source while the data period is uniform by adjusting the variable clock in response to detected phase errors. Occasionally, one period of the periodic data is changed by a defined amount. The fixed phase relationship is restored over a number of periods in a gradual manner by changing the frequency of the variable clock by an amount. By restoring the phase relationship gradually, quality degradation of the transmitted signal is reduced.

Abstract: A novel and useful apparatus for and method of reducing phase and amplitude modulation bandwidth in polar transmitters. The bandwidth reduction mechanism of the present invention effectively reduces the phase modulation bandwidth of the polar modulation performed in the transmitter by modifying the zero-crossing trajectories in the IQ domain. This significantly reduces the phase modulation bandwidth while still meeting the output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as 3G WCDMA, etc. The mechanism detects a zero crossing or a near zero crossing within a predetermined threshold of the origin and an offset vector is generated that when added to the input TX IQ data, shifts the trajectory to avoid the origin thus reducing the resultant polar modulation amplitude and phase bandwidth.

Abstract: Techniques are disclosed relating to reducing wander created by AC couplers. In one embodiment, an integrated circuit is disclosed that includes an AC coupler and a DC-level shifter. The AC coupler is configured to receive a differential input signal at first and second nodes, and to shift a common-mode voltage of the differential input signal. The DC-level shifter is coupled to the first and second nodes, and configured to reduce wander of the AC coupler. In various embodiments, the DC-level shifter is configured to supply a differential reference signal to the AC coupler, and to create the differential reference signal from the differential input signal at the first and second nodes by changing a common-mode voltage of the differential input signal.

Abstract: An apparatus includes a capacitor coupled between a first node responsive to receive an input signal and a second node. The apparatus includes a first circuit coupled to the second node and a third node. The first circuit is selectively operable to separately configure at least one of a low-frequency gain of an equalizer and a pole of the equalizer. The equalizer includes the first circuit and the capacitor. The second node is responsive to receive an equalized version of an AC signal of the input signal in a first mode of the apparatus. The second node is responsive to receive a non-equalized version of the AC signal of the input signal in a second mode of the apparatus. The equalized version of the AC signal of the input signal may be a level-shifted and equalized version of the AC signal in the first mode of the apparatus.

Abstract: The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.

Abstract: Circuitry and methods for supporting serial communications over serial interconnects between circuit modules are provided. A data recovery circuit receives incoming serial data from the serial interconnect path with zero delay. The data recovery circuit includes a data sampler that samples the incoming serial data using a multiphase clock. Data samples are provided to a multiplexer that selects an optimum sampled data signal to use as a recovered data signal. The multiplexer has a control input that receives a phase pointer signal. Control circuitry in the data recovery circuit analyzes the sampled data signals and a current value of the phase pointer to compute a clock phase shift error. If the clock phase shift error exceeds a predetermined value, the phase pointer signal can be updated. The data recovery circuit may be implemented using hardwired circuitry or programmable logic.