Patents by Inventor Jisu Kim
Jisu Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150027905Abstract: The present invention relates to a composition which reduces the measurement error caused by the effect of hematocrit in a biosensor and to a biosensor comprising the same. Specifically, the invention relates to a reagent composition comprising an enzyme, an electron transfer mediator, a water-soluble polymer, and bile acid, and to a biosensor comprising a reagent layer formed of the composition. The reagent layer reduces the measurement error caused by the effect of hematocrit in the biosensor.Type: ApplicationFiled: March 6, 2012Publication date: January 29, 2015Applicant: LG ELECTRONICS INC.Inventors: Jisu Kim, Gueisam Lim
-
Publication number: 20140269031Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Taehui Na, Jisu Kim, Seung H. Kang, Jung Pill Kim
-
Patent number: 8717811Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.Type: GrantFiled: March 5, 2013Date of Patent: May 6, 2014Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
-
Patent number: 8693272Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier.Type: GrantFiled: June 30, 2011Date of Patent: April 8, 2014Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Seung H. Kang
-
Patent number: 8670266Abstract: A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.Type: GrantFiled: January 30, 2012Date of Patent: March 11, 2014Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Kyungho Ryu, Youngdon Jung, Jisu Kim, Jung Pill Kim, Seung H. Kang
-
Patent number: 8611132Abstract: A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.Type: GrantFiled: January 9, 2012Date of Patent: December 17, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Jisu Kim, Youngdon Jung, Jung Pill Kim, Seung H. Kang
-
Publication number: 20130323827Abstract: A biochip including conductive particle and a device for detecting target antigen comprising the biochip are disclosed. According to the present invention, a target antigen can be effectively detected using a small amount of target antigen alone, whereby nonspecific detection signal can be reduced and an amplified signal can be detected.Type: ApplicationFiled: February 7, 2012Publication date: December 5, 2013Applicant: LG ELECTRONICS INC.Inventors: Kyuho Song, Sunkil Kang, Dayeon Kang, Taeyoung Kim, Seungmok Han, Gueisam Lim, Jisu Kim
-
Publication number: 20130286721Abstract: A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.Type: ApplicationFiled: September 13, 2012Publication date: October 31, 2013Applicants: Industry Academic Cooperation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Youngdon Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
-
Patent number: 8531902Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.Type: GrantFiled: June 30, 2011Date of Patent: September 10, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung H. Kang
-
Publication number: 20130194862Abstract: A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.Type: ApplicationFiled: January 30, 2012Publication date: August 1, 2013Applicant: QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Kyungho Ryu, Youngdon Jung, Jisu Kim, Jung Pill Kim, Seung H. Kang
-
Patent number: 8432727Abstract: In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.Type: GrantFiled: April 29, 2010Date of Patent: April 30, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, YonseiInventors: Kyungho Ryu, Jisu Kim, Seong-Ook Jung, Seung H. Kang
-
Patent number: 8423329Abstract: Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor.Type: GrantFiled: January 21, 2010Date of Patent: April 16, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, YonseiInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang
-
Patent number: 8406064Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.Type: GrantFiled: July 30, 2010Date of Patent: March 26, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang
-
Publication number: 20130002352Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Seung H. Kang
-
Publication number: 20130003447Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung H. Kang
-
Patent number: 8335101Abstract: A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor and the second load transistor are input and output (I/O) transistors adapted to operate at a load supply voltage similar to a core supply voltage of a core transistor within the circuit.Type: GrantFiled: January 21, 2010Date of Patent: December 18, 2012Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Seung H. Kang
-
Publication number: 20120275212Abstract: A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.Type: ApplicationFiled: January 9, 2012Publication date: November 1, 2012Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Jisu Kim, Youngdon Jung, Jung Pill Kim, Seung H. Kang
-
Patent number: 8161430Abstract: Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.Type: GrantFiled: April 22, 2008Date of Patent: April 17, 2012Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon
-
Patent number: 8154903Abstract: A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and to a second split path including a second load transistor. The second path is coupled to a third split path including a third load transistor and to a fourth split path including a fourth load transistor.Type: GrantFiled: June 17, 2009Date of Patent: April 10, 2012Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Seung H. Kang
-
Publication number: 20120026783Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang