Patents by Inventor Jitendra Kumar

Jitendra Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134829
    Abstract: A method for processing data, comprising receiving a folder attached request at a virtual media service operating on a processor, creating a virtual image data file and lookup table in response to the folder attached request at the virtual media service, preparing content to be populated into a master boot record region in response to the folder attached request and generating a virtual USB device in response to the populated master boot record.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Applicant: DELL PRODUCTS L.P.
    Inventors: Jitendra Kumar, Rajeshkumar Ichchhubhai Patel, Lakshmi Satya Sai Sindhu Karri
  • Patent number: 11949370
    Abstract: A pier for a solar tracking system includes a bearing housing assembly, a frame, the frame defining an A-profile having a pair of legs and a crown at a center portion thereof, and a mounting bracket, the mounting bracket coupled to a portion of the crown of the frame at a first portion thereof and coupled to a portion of the bearing housing assembly at a second portion thereof.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: April 2, 2024
    Assignee: NEXTRACKER LLC
    Inventors: Phani Kumar, Abhimanyu Sable, Jitendra Morankar, Alexander W. Au, David Kresse
  • Publication number: 20240105508
    Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Jitendra Kumar Jha, Justin Mueller, Nazila Haratipour, Gilbert W. Dewey, Chi-Hing Choi, Jack T. Kavalieros, Siddharth Chouksey, Nancy Zelick, Jean-Philippe Turmaud, I-Cheng Tung, Blake Bluestein
  • Publication number: 20240104563
    Abstract: Disclosed are various embodiments for a service for decentralized browser based wallets. Various embodiments of the present disclosure can receive a first passcode and a second passcode from a security provider device. Various embodiments can use a cryptowallet to decrypt a first encrypted private key using the first passcode to generate a decrypted private key. Various embodiments can use a cryptowallet to sign a transaction request with the decrypted private key. Various embodiments can use a cryptowallet to generate a second encrypted private key by encrypting the decrypted private key using the second passcode.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Jitendra Singh Dikhit, Alaric M. Eby, Andras L. Ferenczi, Ashish Kumar, Upendra Mardikar
  • Publication number: 20240097186
    Abstract: An EB-PVD technique was used to fabricate ceramic/polymer/ceramic (LAGP/PE/LAGP) hybrid separator for rechargeable LIBs and Li batteries. The application of a ceramic electrolyte (LAGP) layer on traditional PE separator soaked in 1-M LiAsF6 liquid electrolyte combined the best attributes of traditional PE separator and solid inorganic electrolytes. The synergistic behavior of hybrid separator resulted in a high mechanical stability/flexibility, increased liquid uptake, high ion conduction, reduced cell voltage polarization, no lithium dendrite formation, and increased usable lithium content as compared to the state-of-the-art PE separator used in LIBs. The functional separator can be used to prolong life cycle and power capability of present LIBs. Thickness and density optimization of LAGP or similar electrolytes on polymer or other battery separators and their use in full Li battery (LIB, Li—S, Li—O2, Li-Ph, flow battery) cells are expected to further improve performance.
    Type: Application
    Filed: April 14, 2023
    Publication date: March 21, 2024
    Inventors: Jitendra Kumar, Guru Subramanyam
  • Publication number: 20240076008
    Abstract: A throttle control and safety switch device that serves the dual function of adjusting a throttle of an ATV (all-terrain vehicle) while turning off the engine in the event of failure of a throttle cable or if the throttle cable is stuck, is disclosed. The throttle control and safety switch device includes an operating lever connected to a pivot shaft for pivotal movement about an axis (A-A?). A first carrier connected to the pivot shaft includes a safety switch and a cable attachment portion to engage a throttle actuating cable. The safety switch transmits a cutoff signal to an electronic control unit (ECU) upon actuation by a plunger portion of a second carrier pivotally connected to the pivot shaft via fastener and connected to the first carrier via a dowel and slot arrangement.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 7, 2024
    Applicant: UNO Minda Limited
    Inventors: Tarun MALHOTRA, Shwetaank SHARMA, Jitendra Kumar SAINI
  • Patent number: 11923290
    Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Siddharth Chouksey, Gilbert Dewey, Nazila Haratipour, Mengcheng Lu, Jitendra Kumar Jha, Jack T. Kavalieros, Matthew V. Metz, Scott B Clendenning, Eric Charles Mattson
  • Patent number: 11918218
    Abstract: An end effector for use with a surgical stapler includes a staple cartridge assembly movable relative to an anvil assembly. The staple cartridge assembly defines a plurality of retention slots and a cavity. The staple cartridge assembly includes a plurality of staples, a plurality of pushers, an actuation sled, a surgical buttress material, a suture, and an anchoring button. The actuation sled is configured for movement along a length of the staple cartridge assembly to sequentially engage the plurality of pushers to eject the plurality of staples through the respective plurality of retention slots. The anchoring button is configured to be received in the cavity of the staple cartridge assembly such that a portion of the suture is supported in the cavity to be severed by a knife blade of the actuation sled when the actuation sled is advanced distally.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: March 5, 2024
    Assignee: COVIDIEN LP
    Inventors: Roanit Fernandes, Suresh Kumar Prema Mohanasundaram, Jitendra Bhargava Srinivas, Matthew J. Chowaniec
  • Patent number: 11907630
    Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: February 20, 2024
    Assignee: Synopsys, Inc.
    Inventors: Jitendra Kumar Gupta, Alexander John Wakefield
  • Publication number: 20240056589
    Abstract: Disclosed are apparatuses, systems, and techniques that improve memory and computational efficiency of remote direct memory accesses into a memory of a graphics processing unit. The techniques include but are not limited to receiving packets with video frame data, storing the plurality of packets in a memory of a network controller, processing the packets to obtain unit(s) of the video frame, storing the unit(s) representative of the video frame in a memory of a graphics processing unit (GPU), and extracting the data of the video frame from the units representative of the video frame, stored in the memory of the GPU, to render the video frame.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Jitendra Kumar, Tushar Khinvasara, Bhushan Rupde, Kaustubh Purandare
  • Publication number: 20240053973
    Abstract: Various systems and methods are described for deployment, import, and scheduling of containers and other software components on cloud and edge computing hardware. A development platform may receive, from a remote location, package data for a deployment of one or more containers, including a configuration for the one or more containers. Such package data may be provided by a Helm chart or a Docker Compose YAML file. The development platform may extract the configuration for the one or more containers from the package data, and also perform a security evaluation of the one or more containers and the configuration for the one or more containers to validate compliance with a security policy. The development platform may execute (and coordinate scheduling) of one or more container images for the one or more containers, based on the configuration, after validating compliance with the security policy.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 15, 2024
    Inventors: Vidya Ranganathan, Aditya Shukla, Nitesh Kumar, Jitendra Kumar Saini
  • Patent number: 11876521
    Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: January 16, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hajee Mohammed Shuaeb Fazeel, Jitendra Kumar Yadav, Thomas Evan Wilson
  • Publication number: 20240006533
    Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.
    Type: Application
    Filed: July 2, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Siddharth Chouksey, Nazila Haratipour, Christopher Jezewski, Jitendra Kumar Jha, Ilya V. Karpov, Matthew V. Metz, Arnab Sen Gupta, I-Cheng Tung, Nancy Zelick, Chi-Hing Choi, Dan S. Lavric
  • Publication number: 20240006488
    Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, David Kohen, Natalie Briggs, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
  • Publication number: 20240006494
    Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
  • Publication number: 20240006506
    Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.
    Type: Application
    Filed: July 2, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Siddharth Chouksey, Nazila Haratipour, Christopher Jezewski, Jitendra Kumar Jha, Ilya V. Karpov, Jack T. Kavalieros, Arnab Sen Gupta, I-Cheng Tung, Nancy Zelick, Chi-Hing Choi, Dan S. Lavric
  • Patent number: 11847082
    Abstract: An Information Handling System (IHS) includes multiple hardware devices, and a Baseboard Management Controller (BMC) in communication with the hardware devices. The BMC includes executable code to cause the BMC to receive a message associated with a non-registered hardware device that is not registered to be managed by the BMC in which the message formatted according to a native protocol of the BMC. The code further causes the code to transmit the message to a device plugin associated with the non-registered hardware device in which the device plugin comprises custom instructions that, upon execution by a system processor, cause the IHS to convert the message into a protocol associated with the non-registered hardware device, and forward the converted message to the non-registered hardware device using the protocol of the non-registered hardware device.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: December 19, 2023
    Assignee: Dell Products L.P.
    Inventors: Chandrasekhar Puthillathe, Chitrak Gupta, Raghavendra Venkataramudu, Chinmay Shripad Hegde, Anurag Sharma, Rajib Saha, Jitendra Kumar Rath
  • Publication number: 20230384910
    Abstract: A system includes a computing device that includes a memory configured to store instructions. The computing device also includes a processor to execute the instructions to perform operations that include receiving data representing one or more user-selected item attributes. The data includes one of at least four selectable interest levels for each of the one or more user-selected item attributes. Operations also include identifying one or more items representative of the selected interest level for each of the one or more user-selected item attributes, and initiating delivery of data representing the identified one or more items for user selection.
    Type: Application
    Filed: December 23, 2022
    Publication date: November 30, 2023
    Inventors: Sampo Juhani Kaasila, Jitendra Kumar Bansal, Prince Dhiman, Mayur G. Warialani
  • Patent number: 11806205
    Abstract: An oropharyngeal dam for facilitating a safe and efficient dental treatment is disclosed. The oropharyngeal dam includes a pair of cheek retractors including an upper retractor component, a lower retractor component and a cheek retracting sheet. Further, the upper retractor component, the lower retractor component, the cheek retracting sheet, and a set of lip retractors are collectively configured to retract cheeks of a patient. The oropharyngeal dam includes a tongue protector including an upper protector component, a lower protector component and a tongue protecting sheet. Furthermore, the upper protector component, the lower protector component and the tongue protecting sheet are collectively configured to shield and retract a tongue of the patient. The set of lip retractors are configured to aid lip retraction when pulled outside the mouth.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: November 7, 2023
    Inventors: Neha Jain, Shrikanth Sali, Jitendra Kumar
  • Publication number: 20230353758
    Abstract: A system and method for converting raw frame data to a video file. Instead of converting all raw frame raw for each frame, embodiments create a mapping table and compare a mapping of the raw frame data for a current frame with a mapping of the raw frame data for a previous frame to determine if raw frame data changed from a previous frame to the current frame. Embodiments convert only the new raw frame data and update the mapping table with the new raw frame data, whereby the processing resources and time needed to convert raw frame data into a video file may be greatly reduced.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Inventors: JITENDRA KUMAR, SOOREJ PONNANDI, RAJESHKUMAR ICHCHHUBHAI PATEL, MOHANA MURALI GURRAM, B. BALAJI SINGH