Patents by Inventor Jitsuo Kanazawa
Jitsuo Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7671468Abstract: A light emitting apparatus is comprised of a multilayer chip varistor having a varistor element body, a semiconductor light emitting element, and a reflecting portion. The varistor element body includes a varistor layer, and a plurality of internal electrodes opposed to each other so as to interpose the varistor layer between the internal electrodes. The semiconductor light emitting element is disposed on the multilayer chip varistor and is electrically connected to the plurality of internal electrodes so as to be connected in parallel to the multilayer chip varistor. The reflecting portion is disposed between the multilayer chip varistor and the semiconductor light emitting element. The reflecting portion reflects light traveling toward the multilayer chip varistor out of light generated by the semiconductor light emitting element.Type: GrantFiled: September 5, 2006Date of Patent: March 2, 2010Assignee: TDK CorporationInventors: Jitsuo Kanazawa, Yo Saito, Kimio Suto
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Patent number: 7505239Abstract: A light emitting device has a semiconductor light emitting element and a multilayer chip varistor. The multilayer chip varistor has a multilayer body with a varistor portion therein, and a plurality of external electrodes disposed on an outer surface of the multilayer body. The varistor portion has a varistor layer containing ZnO as a principal component and exhibiting nonlinear voltage-current characteristics, and a plurality of internal electrodes arranged to interpose the varistor layer between them. Each of the external electrodes is connected to a corresponding internal electrode out of the plurality of internal electrodes. The semiconductor light emitting element is disposed on the multilayer chip varistor. The semiconductor light emitting element is connected to corresponding external electrodes out of the plurality of external electrodes so as to be connected in parallel to the varistor portion.Type: GrantFiled: April 13, 2006Date of Patent: March 17, 2009Assignee: TDK CorporationInventors: Jitsuo Kanazawa, Nobuei Shimojo, Dai Matsuoka, Kimio Suto, Makoto Numata, Yo Saito
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Patent number: 7355251Abstract: An object is to provide a light emitting device capable of efficiently dissipating heat generated in a semiconductor light-emitting element.Type: GrantFiled: October 4, 2006Date of Patent: April 8, 2008Assignee: TDK CorporationInventors: Jitsuo Kanazawa, Yo Saito
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Publication number: 20070081288Abstract: An object is to provide a light emitting device capable of efficiently dissipating heat generated in a semiconductor light-emitting element.Type: ApplicationFiled: October 4, 2006Publication date: April 12, 2007Applicant: TDK CORPORATIONInventors: Jitsuo Kanazawa, Yo Saito
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Publication number: 20070075323Abstract: A light emitting apparatus is comprised of a multilayer chip varistor having a varistor element body, a semiconductor light emitting element, and a reflecting portion. The varistor element body includes a varistor layer, and a plurality of internal electrodes opposed to each other so as to interpose the varistor layer between the internal electrodes. The semiconductor light emitting element is disposed on the multilayer chip varistor and is electrically connected to the plurality of internal electrodes so as to be connected in parallel to the multilayer chip varistor. The reflecting portion is disposed between the multilayer chip varistor and the semiconductor light emitting element. The reflecting portion reflects light traveling toward the multilayer chip varistor out of light generated by the semiconductor light emitting element.Type: ApplicationFiled: September 5, 2006Publication date: April 5, 2007Applicant: TDK CORPORATIONInventors: Jitsuo Kanazawa, Yo Saito, Kimio Suto
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Publication number: 20060232373Abstract: A light emitting device has a semiconductor light emitting element and a multilayer chip varistor. The multilayer chip varistor has a multilayer body with a varistor portion therein, and a plurality of external electrodes disposed on an outer surface of the multilayer body. The varistor portion has a varistor layer containing ZnO as a principal component and exhibiting nonlinear voltage-current characteristics, and a plurality of internal electrodes arranged to interpose the varistor layer between them. Each of the external electrodes is connected to a corresponding internal electrode out of the plurality of internal electrodes. The semiconductor light emitting element is disposed on the multilayer chip varistor. The semiconductor light emitting element is connected to corresponding external electrodes out of the plurality of external electrodes so as to be connected in parallel to the varistor portion.Type: ApplicationFiled: April 13, 2006Publication date: October 19, 2006Applicant: TDK CORPORATIONInventors: Jitsuo Kanazawa, Nobuei Shimojo, Dai Matsuoka, Kimio Suto, Makoto Numata, Yo Saito
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Patent number: 6749183Abstract: A water treatment apparatus including a mixing bath having an open portion where a carbonic acid gas intermixed with water to be treated by the water treatment apparatus and dissolved oxygen excluded from the water to be treated are discharged. The water treatment apparatus also includes water storage tank separate from the mixing bath and in which treated water from the mixing bath is stored.Type: GrantFiled: September 11, 2002Date of Patent: June 15, 2004Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto
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Patent number: 6730858Abstract: A circuit board for mounting a part having a plurality of bumps by ultrasonic bonding. The circuit board includes a main body and a conductive layer provided on the main body. The conductive layer has a conductive pattern having at least one bonding area configured to correspond to the plurality of bumps of the part. The conductive layer has an isolated notch part located proximate the at least one bonding area.Type: GrantFiled: July 21, 1998Date of Patent: May 4, 2004Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto, Kenji Honda
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Patent number: 6565687Abstract: When connecting electrodes of a chip device CP are ultrasonic-bonded to circuit electrodes provided for a resin substrate 10 to mount the chip device CP on the resin substrate 10, a heater 5 for heating the resin substrate 10 is provided with which the temperature of the resin substrate 10 is raised to a level with which the ratio of elastic modulus &egr;h realized when heat is supplied with respect to elastic modulus &egr;r of the resin substrate 10 at room temperature satisfies 1>&egr;h/&egr;r≧0.5. The heater 5 may be provided for the substrate retaining frame 4.Type: GrantFiled: July 10, 2002Date of Patent: May 20, 2003Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Hiroki Hara
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Publication number: 20030029543Abstract: When connecting electrodes of a chip device CP are ultrasonic-bonded to circuit electrodes provided for a resin substrate 10 to mount the chip device CP on the resin substrate 10, a heater 5 for heating the resin substrate 10 is provided with which the temperature of the resin substrate 10 is raised to a level with which the ratio of elastic modulus &egr;h realized when heat is supplied with respect to elastic modulus &egr;r of the resin substrate 10 at room temperature satisfies 1>&egr;h/&egr;r≧0.5. The heater 5 may be provided for the substrate retaining frame 4.Type: ApplicationFiled: July 10, 2002Publication date: February 13, 2003Applicant: TDK Corp.Inventors: Masashi Gotoh, Jitsuo Kanazawa, Hiroki Hara
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Publication number: 20030006513Abstract: A production method of an electronic part comprising a step o working a substrate having formed thereon a metal thin-film conductor using water, wherein said water satisfies the relations 3.5≦pH≦6.5 and DO≦0.5 pH2−6.5 pH+22 [wherein DO represents a dissolved oxygen amount (unit ppm)].Type: ApplicationFiled: September 11, 2002Publication date: January 9, 2003Applicant: TDK CORPORATIONInventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto
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Patent number: 6471783Abstract: A production method of an electronic part comprising a step o working a substrate having formed thereon a metal thin-film conductor using water, wherein said water satisfies the relations 3.5≦pH≦6.5 and DO≦0.5 pH2−6.5 pH+22 [wherein DO represents a dissolved oxygen amount (unit ppm)]. By using the water in the case of working substrates in the production steps of electronic parts, the generations of the static electricity and the oxidation caused by water used for working are restrained. The present invention is particularly effective in working of an electronic part wherein a metal thin-film conductor containing at least two kinds of metals including Al on a substrate having a pyroelectric property.Type: GrantFiled: May 19, 1999Date of Patent: October 29, 2002Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto
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Patent number: 6460591Abstract: When connecting electrodes of a chip device CP are ultrasonic-bonded to circuit electrodes provided for a resin substrate 10 to mount the chip device CP on the resin substrate 10, a heater 5 for heating the resin substrate 10 is provided with which the temperature of the resin substrate 10 is raised to a level with which the ratio of elastic modulus &egr;h realized when heat is supplied with respect to elastic modulus &egr;r of the resin substrate 10 at room temperature satisfies 1>&egr;h/&egr;r≧0.5. The heater 5 may be provided for the substrate retaining frame 4.Type: GrantFiled: April 6, 2000Date of Patent: October 8, 2002Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Hiroki Hara
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Patent number: 6417026Abstract: In a chip device in which not only an electrode pattern 25 is provided on a main mounting surface 21a of a base 21 but also bump electrodes 22 are provided as external electrodes for face-down mounting, an electrically insulating layer 31 is provided to be put on at least a part of the main mounting surface 21a so as to remain edge portions which do not cover at least a part of the electrode pattern 25, and a protection layer 32 for protecting the main mounting surface is further provided at a distance from the main mounting surface 21a so as to be put on the electrically insulating layer 31, so that the bump electrodes 22 are connected to the electrode pattern 25 while being in contact with the edge portions of the electrically insulating layer 31 and the protection layer 32.Type: GrantFiled: January 5, 2001Date of Patent: July 9, 2002Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Hajime Kuwajima
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Patent number: 6382495Abstract: A chip junction nozzle in that opposite slant planes 43 which come into contact with edges of 2 sides of the chip in parallel centering around a nozzle center, and a vacuum suction hole 42 opened in the nozzle center are provided, and the slant plane 43 is formed into a mirror surface having the surface hardness more than HrC40. Further, when the surface roughness of the mirror surface is expressed by the average roughness of the center line, the average roughness of the center line is not more than 1.6 &mgr;m.Type: GrantFiled: February 1, 2001Date of Patent: May 7, 2002Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Koichiro Okazaki, Toru Mizuno, Yoshihiro Onozeki
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Publication number: 20020014687Abstract: An electronic part in which a chip 2 having bump electrodes is sealed in a cavity 14 of a resin container 10, wherein the resin container having: a mounting board 1 having a conductor pattern 4 for bump-mounting the chip 2; an intermediate board 5 overlaid on the mounting board 1 and having a window for forming an inner wall apart from the chip 2 for predetermined distances; a cover board overlaid on the intermediate board 5 to cover the window; a first adhesive layer 8 which is interposed between overlaid portions of the mounting board 1 and the intermediate board 5; and a second adhesive layer 9 which is interposed between overlaid portion of the intermediate board 5 and the cover board 7, wherein the first and second adhesive layers 8 and 9 between which the intermediate board 5 is interposed are heated and pressed at a time in a direction of the thickness of each of the mounting board 1 and the cover board 7, and the mounting board 1, the intermediate board 5 and the cover board 7 are brought into intimatType: ApplicationFiled: September 20, 2001Publication date: February 7, 2002Applicant: TDK CORPORATIONInventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto
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Patent number: 6320739Abstract: An electronic part in which a chip 2 having bump electrodes is sealed in a cavity 14 of a resin container 10, wherein the resin container having: a mounting board 1 having a conductor pattern 4 for bump-mounting the chip 2; an intermediate board 5 overlaid on the mounting board 1 and having a window for forming an inner wall apart from the chip 2 for predetermined distances; a cover board overlaid on the intermediate board 5 to cover the window; a first adhesive layer 8 which is interposed between overlaid portions of the mounting board 1 and the intermediate board 5; and a second adhesive layer 9 which is interposed between overlaid portion of the intermediate board 5 and the cover board 7, wherein the first and second adhesive layers 8 and 9 between which the intermediate board 5 is interposed are heated and pressed at a time in a direction of the thickness of each of the mounting board 1 and the cover board 7, and the mounting board 1, the intermediate board 5 and the cover board 7 are brought into intimatType: GrantFiled: April 16, 1999Date of Patent: November 20, 2001Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto
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Publication number: 20010018982Abstract: A circuit board which comprises a conductive pattern section 4 with a pattern formed on a conductive layer 3 provided on a board main body 2, wherein two or more bonding positions 6a, 6b, 6c that bumps of a part mounted by ultrasonic bonding strike are set in the conductive pattern section 4, characterized in that a notch part 8a or a recess extending from the margin of the conductive pattern section 4 to the inside thereof and reaching the proximity of the bonding position or an isolated notch part 8b or recess is formed in the conductive layer in the proximity of at least one bonding position.Type: ApplicationFiled: July 21, 1998Publication date: September 6, 2001Inventors: MASASHI GOTOH, JITSUO KANAZAWA, SYUICHIRO YAMAMOTO, KENJI HONDA
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Patent number: 6282781Abstract: A resin package fabrication processes comprises three steps. At the first step, a thermosetting resin-containing resin substrate is machined. At the second step carried out after the first step, the resin substrate is heated to an original glass transition temperature that the resin substrate has or a temperature that is higher than the glass transition temperature so that the glass transition temperature that the resin substrate has is elevated to a new glass transition temperature. At the third step, a resin layer is placed on at least a portion of the resin substrate to which the new glass transition temperature is imparted, and the resin substrate with the resin layer placed on that portion is then heated to the original glass transition temperature or a temperature between the original glass transition temperature and the new glass transition temperature, thereby fixing the resin layer to the resin substrate.Type: GrantFiled: December 17, 1998Date of Patent: September 4, 2001Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto
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Patent number: 6281436Abstract: An electronic element is mounted on a resin wiring substrate and a cover member is bonded to the wiring substrate so as to cover the electronic element and constitute an encapsulation region. The encapsulation region houses the electronic element and has a cavity inside. A side electrode is formed of an electronically conductive through groove provided in a cover-member-bonding surface on the wiring substrate. A plating layer inside the electrically conductive through groove includes at least two metal layers including an Au plating layer and a Cu plating layer. The plating layer has conductors connected to circumferential peripheries of the electrically conductive through groove on upper and lower surfaces of the wiring substrate. Only the Cu plating layer is formed on the conductor on the upper surface of the wiring substrate to improve the reliability of bonding.Type: GrantFiled: February 7, 2000Date of Patent: August 28, 2001Assignee: TDK CorporationInventors: Masashi Gotoh, Jitsuo Kanazawa, Shuichiro Yamamoto