Patents by Inventor Jitsuo Kanazawa

Jitsuo Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010011668
    Abstract: A chip junction nozzle in that opposite slant planes 43 which come into contact with edges of 2 sides of the chip in parallel centering around a nozzle center, and a vacuum suction hole 42 opened in the nozzle center are provided, and the slant plane 43 is formed into a mirror surface having the surface hardness more than HrC40. Further, when the surface roughness of the mirror surface is expressed by the average roughness of the center line, the average roughness of the center line is not more than 1.6 &mgr;m.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 9, 2001
    Applicant: TDK CORPORATION 13-1, Nihonbashi 1-chome, Chuo-ku, Tokyo, Japan
    Inventors: Masashi Gotoh, Jitsuo Kanazawa, Koichiro Okazaki, Toru Mizuno, Yoshihiro Onozeki
  • Patent number: 6263565
    Abstract: A through hole 5 formed in a substrate and having an electrode film on an inner surface thereof is cut and divided into two through holes or blind holes each of substantially semicircular arc shape through dicing processing using a rotating blade, and one of the-divided through holes 5 of substantially semicircular arc shape is used as an external connection terminal 3 of substantially semicircular concave arc shape thereby to form a surface mounted electronic parts having a plurality of the external connection terminals 3. The height H of the substantially semicircular arc formed at an inner surface of each of the external connection terminals is set to be equal to or smaller than a value obtained by subtracting twice a thickness t of the electrode film from a radius R of a curvature of the arc.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: July 24, 2001
    Assignee: TDK Corporation
    Inventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto, Kenji Honda
  • Publication number: 20010001293
    Abstract: In a chip device in which not only an electrode pattern 25 is provided on a main mounting surface 21a of a base 21 but also bump electrodes 22 are provided as external electrodes for face-down mounting, an electrically insulating layer 31 is provided to be put on at least a part of the main mounting surface 21a so as to remain edge portions which do not cover at least a part of the electrode pattern 25, and a protection layer 32 for protecting the main mounting surface is further provided at a distance from the main mounting surface 21a so as to be put on the electrically insulating layer 31, so that the bump electrodes 22 are connected to the electrode pattern 25 while being in contact with the edge portions of the electrically insulating layer 31 and the protection layer 32.
    Type: Application
    Filed: January 5, 2001
    Publication date: May 17, 2001
    Applicant: TDK CORPORATION
    Inventors: Masashi Gotoh, Jitsuo Kanazawa, Hajime Kuwajima
  • Patent number: 6204454
    Abstract: A wiring board having a conductor layer formed on a substrate and a connecting pad disposed in a connecting pad disposition portion provided in part of the conductor layer surface, the conductor layer having a resin inflow prevention portion which is provided adjacently to the said connecting pad disposition portion and which has a surface roughness greater than the surface roughness of the said connecting pad disposition portion, the resin inflow prevention portion being capable of overcoming the problem of prior art that an adhesive resin (resin layer) of a prepreg or an adhesive flows out onto the upper surface of the pad, due to its softening under heat and its being pressurized for bonding when a structure member such as a cover layer is bonded to the wiring board, and forms a cured resin which extremely inhibits the bonding property of a chip element onto the pad.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: March 20, 2001
    Assignee: TDK Corporation
    Inventors: Masashi Gotoh, Jitsuo Kanazawa, Syuichiro Yamamoto
  • Patent number: 6189760
    Abstract: A chip junction nozzle in that opposite slant planes 43 which come into contact with edges of 2 sides of the chip in parallel centering around a nozzle center, and a vacuum suction hole 42 opened in the nozzle center are provided, and the slant plane 43 is formed into a mirror surface having the surface hardness more than HrC40. Further, when the surface roughness of the mirror surface is expressed by the average roughness of the center line, the average roughness of the center line is not more than 1.6 &mgr;m.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: February 20, 2001
    Assignee: TDK Corporation
    Inventors: Masashi Gotoh, Jitsuo Kanazawa, Koichiro Okazaki, Toru Mizuno, Yoshihiro Onozeki
  • Patent number: 6181015
    Abstract: In a chip device in which not only an electrode pattern 25 is provided on a main mounting surface 21a of a base 21 but also bump electrodes 22 are provided as external electrodes for face-down mounting, an electrically insulating layer 31 is provided to be put on at least a part of the main mounting surface 21a so as to remain edge portions which do not cover at least a part of the electrode pattern 25, and a protection layer 32 for protecting the main mounting surface is further provided at a distance from the main mounting surface 21a so as to be put on the electrically insulating layer 31, so that the bump electrodes 22 are connected to the electrode pattern 25 while being in contact with the edge portions of the electrically insulating layer 31 and the protection layer 32.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: January 30, 2001
    Assignee: TDK Corporation
    Inventors: Masashi Gotoh, Jitsuo Kanazawa, Hajime Kuwajima
  • Patent number: 4510813
    Abstract: A temperature compensation circuit for strain gauges fixed to an object to be measured and adapted to take out an output conforming to a strain by being fed with a constant voltage, wherein a compensation resistors in the form of a combination of two or more kinds of resistors each made of a pure single metal material having a resistance versus temperature characteristic equivalent to the output voltage versus temperature characteristic of the bridge circuit of strain gauges are inserted and connected at a predetermined position on the voltage supply side or output take-out side of the bridge circuit of strain gauges thereby compensating for variations in the strain gauge output due to temperature variations with high accuracy. The temperature compensation circuit for strain gauges according to the present invention not only has very high accuracy of temperature compensation but also can be produced with high yield.
    Type: Grant
    Filed: December 9, 1982
    Date of Patent: April 16, 1985
    Assignee: Kabushiki Kaisha Ishida Koki Seisakusho
    Inventor: Jitsuo Kanazawa