Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Abstract: A method of backlight control for a display panel is provided. The display panel is configured to display with a variable refresh rate in a plurality of frame periods each having a fixed period and a variable period. The method includes steps of: generating a first backlight control signal in the fixed period of a frame period; determining whether a liquid crystal (LC) transition time corresponding to the frame period ends before an end time of the variable period of the frame period; generating a second backlight control signal in the variable period of the frame period when the LC transition time ends before the end time of the variable period of the frame period; and generating a compensation backlight control signal in a next frame period according to a backlight duty cycle of the frame period.

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Abstract: In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a

Abstract: A bond head is provided. The bond head includes a bond base, a chuck member, and an elastic material. The chuck member protrudes from a surface of the bond base, and has a chuck surface formed with vacuum holes for holding a die using differential air pressure. In the direction parallel to the chuck surface, the width of the chuck surface is less than the width of the bond base and is equal to or greater than the width of the die. The elastic material is disposed over the chuck surface. The elastic material is arranged around the periphery of the chuck surface to cover edges and/or corners of the chuck surface.

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

Abstract: Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures.

Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

Abstract: A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

Abstract: In an embodiment, a method for manufacturing a semiconductor device includes forming a redistribution structure on a carrier substrate, connecting a plurality of core substrates physically and electrically to the redistribution structure with a first anisotropic conductive film, the first anisotropic conductive film including a dielectric material and conductive particles, and pressing the plurality of core substrates and the redistribution structure together to form conductive paths between the plurality of core substrates and the redistribution structure with the conductive particles in the first anisotropic conductive film. The method also includes encapsulating the plurality of core substrates with an encapsulant.

Abstract: A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.