Patents by Inventor Jiunn-Yih Lee
Jiunn-Yih Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9780979Abstract: A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.Type: GrantFiled: January 23, 2017Date of Patent: October 3, 2017Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Kai Sun, Jiunn-Yih Lee, Wen-Cai Lu
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Publication number: 20170222848Abstract: A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.Type: ApplicationFiled: January 23, 2017Publication date: August 3, 2017Inventors: Kai Sun, Jiunn-Yih Lee, Wen-Cai Lu
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Patent number: 9685962Abstract: A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.Type: GrantFiled: July 12, 2016Date of Patent: June 20, 2017Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Meng-Tse Weng, Chun-Wen Yeh, Jiunn-Yih Lee
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Publication number: 20170156338Abstract: Provided is a composite powder used for the visible light catalytic and anti-bacterial purposes. The composite powder includes a plurality of N-type semiconductor particles and a plurality of P-type semiconductor nano-particles. The P-type semiconductor nano-particles cover surfaces of the N-type semiconductor particles respectively. A weight ratio of the N-type semiconductor particles and the P-type semiconductor nano-particles is in a range of 1:0.1 to 1:0.5. A PN junction is provided between each of the N-type semiconductor particles and the corresponding P-type semiconductor nano-particles.Type: ApplicationFiled: March 10, 2016Publication date: June 8, 2017Inventors: Dong-Hau Kuo, Fu-An Yu, Yen-Rong Kuo, Yi-Yuan Yang, Jiunn-Yih Lee, Kuo-Pin Cheng, Chang-Mou Wu, Meng-Wei Ma, Kuan-Ting Chuang
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Patent number: 9673795Abstract: An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.Type: GrantFiled: February 8, 2016Date of Patent: June 6, 2017Assignee: MStar Semiconductor, Inc.Inventors: Meng-Tse Weng, Jiunn-Yih Lee
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Publication number: 20170070230Abstract: A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.Type: ApplicationFiled: July 12, 2016Publication date: March 9, 2017Inventors: Meng-Tse Weng, Chun-Wen Yeh, Jiunn-Yih Lee
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Publication number: 20170070218Abstract: An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.Type: ApplicationFiled: February 8, 2016Publication date: March 9, 2017Inventors: Meng-Tse WENG, Jiunn-Yih LEE
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Patent number: 9514732Abstract: A sound-absorbing material has a membrane having multiple piezoelectric fibers, the fiber density of the membrane is below 50 g/m2, the thickness of the membrane is below 1 mm, sound-absorbing coefficient of the membrane is larger than 0.1 at absorbing frequency at 100 Hz+/?10%, and the sound-absorbing coefficient of the membrane is over 0.05 at absorbing frequency at 800 Hz to 1000 Hz. PVDF electrospinning nanofiber membranes of the present invention are thinner and more flexible compared to conventional sound-absorbing material, the membranes in the present invention performs excellent low frequency sound absorption with very thin membrane.Type: GrantFiled: January 28, 2016Date of Patent: December 6, 2016Assignee: National Taiwan University of Science and TechnologyInventors: Chang-Mou Wu, Min-Hui Chou, Jiunn-Yih Lee
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Publication number: 20160267897Abstract: A sound-absorbing material has a membrane having multiple piezoelectric fibers, the fiber density of the membrane is below 50 g/m2, the thickness of the membrane is below 1 mm, sound-absorbing coefficient of the membrane is larger than 0.1 at absorbing frequency at 100 Hz+/-10%, and the sound-absorbing coefficient of the membrane is over 0.05 at absorbing frequency at 800 Hz to 1000 Hz. PVDF electrospinning nanofiber membranes of the present invention are thinner and more flexible compared to conventional sound-absorbing material, the membranes in the present invention performs excellent low frequency sound absorption with very thin membrane.Type: ApplicationFiled: January 28, 2016Publication date: September 15, 2016Inventors: Chang-Mou Wu, Min-Hui Chou, Jiunn-Yih Lee
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Patent number: 9419786Abstract: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.Type: GrantFiled: March 27, 2015Date of Patent: August 16, 2016Assignee: MStar Semiconductor, Inc.Inventors: Po-Nien Lin, Meng-Tse Weng, Jiunn-Yih Lee
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Patent number: 9276592Abstract: A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.Type: GrantFiled: December 24, 2014Date of Patent: March 1, 2016Assignee: MStar Semiconductor, Inc.Inventors: Po-Nien Lin, Jiunn-Yih Lee
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Patent number: 9166847Abstract: A signal receiving apparatus includes an equalization module, a coarse tuning module and a fine tuning module. The equalization module receives an input signal, and performs an equalization process on the input signal according to an equalization strength to generate an equalized signal. The coarse tuning module adjusts the equalization strength according to the equalized signal until the equalized signal satisfies a preliminary convergence condition. When the preliminary convergence condition is satisfied, the fine tuning module adjusts the equalization strength according to the equalized signal until the equalization strength satisfies a final convergence condition.Type: GrantFiled: January 15, 2015Date of Patent: October 20, 2015Assignee: MSTAR SEMICONDUCTOR, INC.Inventors: Po-Nien Lin, Jyun-Yang Shih, Jiunn-Yih Lee
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Publication number: 20150280761Abstract: A multi-lane serial link signal receiving system includes a clock generating circuit and a plurality of data receiving channels. The clock generating circuit provides a fundamental clock signal. Each of the data receiving channels receives an input signal and the fundamental clock signal, and includes a phase detecting circuit, a multi-order digital clock data recovery circuit and a phase adjusting circuit. The phase detecting circuit samples the input signal according to a sampling clock signal to generate a sampled signal. The multi-order digital clock data recovery circuit performs a digital clock data recovery process on the sampled signal to generate phase adjusting information. The phase adjusting circuit adjusts the phase of the fundamental clock signal according to the phase adjusting information to generate the sampling clock signal.Type: ApplicationFiled: March 27, 2015Publication date: October 1, 2015Inventors: Po-Nien Lin, Meng-Tse Weng, Jiunn-Yih Lee
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Publication number: 20150207652Abstract: A signal receiving apparatus includes an equalization module, a coarse tuning module and a fine tuning module. The equalization module receives an input signal, and performs an equalization process on the input signal according to an equalization strength to generate an equalized signal. The coarse tuning module adjusts the equalization strength according to the equalized signal until the equalized signal satisfies a preliminary convergence condition. When the preliminary convergence condition is satisfied, the fine tuning module adjusts the equalization strength according to the equalized signal until the equalization strength satisfies a final convergence condition.Type: ApplicationFiled: January 15, 2015Publication date: July 23, 2015Inventors: Po-Nien Lin, Jyun-Yang Shih, Jiunn-Yih Lee
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Publication number: 20150188697Abstract: A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.Type: ApplicationFiled: December 24, 2014Publication date: July 2, 2015Inventors: Po-Nien Lin, Jiunn-Yih Lee
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Patent number: 8570071Abstract: A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals.Type: GrantFiled: January 4, 2012Date of Patent: October 29, 2013Assignee: MStar Semiconductor, Inc.Inventor: Jiunn-Yih Lee
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Publication number: 20130043909Abstract: A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals.Type: ApplicationFiled: January 4, 2012Publication date: February 21, 2013Applicant: MStar Semiconductor, Inc.Inventor: Jiunn-Yih LEE
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Publication number: 20110102730Abstract: The invention provides a liquid crystal device. The liquid crystal device includes a first transparent substrate and a second transparent substrate, wherein the first transparent substrate and the second transparent substrate are parallel to each other. Spacers are formed between the first transparent substrate and the second transparent substrate, to define a cavity; and a cholesteric liquid crystal is disposed into the cavity. Particularly, the liquid crystal device is coupled to a supply voltage, and three states of the liquid crystal device are selectively switched by adjusting the voltage, wherein the three states includes a first transparent state, a scattering state and a second transparent state.Type: ApplicationFiled: May 9, 2010Publication date: May 5, 2011Applicant: NATIONAL TAIWAN UNIVERSITYInventors: I-Hui Lee, Yu-Ching Chao, Yu-Chi Chen, Liang-Chao Chang, Chih-Cheng Hsu, Jiunn-Yih Lee, Tien-Lung Chiu, Jiun-Haw Lee
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Patent number: 7668236Abstract: The present invention discloses a multi-stage cable equalizer, comprising a fixed gain device and an adjustable gain device. The fixed gain device compensates the loss caused by the cable at a major band, and the adjustable gain device further compensates the loss at adjusted bands. The multi-stage cable equalizer of the present invention exhibits advantages in design flexibility and reduced cost.Type: GrantFiled: December 5, 2005Date of Patent: February 23, 2010Assignee: Mstar Semiconductor, Inc.Inventor: Jiunn-Yih Lee
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Patent number: 7447511Abstract: A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes.Type: GrantFiled: June 1, 2005Date of Patent: November 4, 2008Assignee: Mstar Semiconductor, Inc.Inventors: Ke-Chiang Huang, Kuo-Feng Hsu, Jiunn-Yih Lee, Hsian-Feng Liu