Abstract: Embodiments are disclosed that allow data to be sent between a Bluetooth enabled device and a virtual device associated with a corresponding physical device. In particular, embodiments of a virtual mobile device system may include one or more components for processing Bluetooth calls where these Bluetooth components may process received Bluetooth calls in a first manner in a connected state and process Bluetooth calls in a disconnected state in a second manner.

Abstract: Embodiments are disclosed that allow encrypted data to be sent between a Bluetooth enabled device and a virtual device associated with a corresponding physical device. In particular, a Bluetooth implementation on the physical device may include one or more raw interfaces to facilitate endpoint to endpoint secure Bluetooth cryptography. Using these raw interfaces, an encrypted Bluetooth channel may be established directly between the virtual device and the Bluetooth enabled device using the radio of the physical device, where data may be encrypted and decrypted at an endpoint of the Bluetooth communication channel (such as at the virtual device or the Bluetooth enabled device) and passed through a Bluetooth implementation on the physical device without any additional encryption or decryption being performed on that data.

Abstract: Embodiments are disclosed that allow encrypted data to be sent between a Bluetooth enabled device and a virtual device associated with a corresponding physical device. In particular, a Bluetooth implementation on the physical device may include one or more raw interfaces to facilitate endpoint to endpoint secure Bluetooth cryptography. Using these raw interfaces, an encrypted Bluetooth channel may be established directly between the virtual device and the Bluetooth enabled device using the radio of the physical device, where data may be encrypted and decrypted at an endpoint of the Bluetooth communication channel (such as at the virtual device or the Bluetooth enabled device) and passed through a Bluetooth implementation on the physical device without any additional encryption or decryption being performed on that data.

Abstract: Embodiments are disclosed that allow encrypted data to be sent between a Bluetooth enabled device and a virtual device associated with a corresponding physical device. In particular, a Bluetooth implementation on the physical device may include one or more raw interfaces to facilitate endpoint to endpoint secure Bluetooth cryptography. Using these raw interfaces, an encrypted Bluetooth channel may be established directly between the virtual device and the Bluetooth enabled device using the radio of the physical device, where data may be encrypted and decrypted at an endpoint of the Bluetooth communication channel (such as at the virtual device or the Bluetooth enabled device) and passed through a Bluetooth implementation on the physical device without any additional encryption or decryption being performed on that data.

Abstract: Systems, apparatuses, and methods for implementing hypervisor post-write notification of processor state register modifications. A write to a state register of the processor may be detected during guest execution. In response to detecting the write to the state register, the processor may trigger microcode to perform the write and copy the new value of the register to a memory location prior to exiting the guest. The hypervisor may be notified of the update to the state register after it occurs, and the hypervisor may be prevented from modifying the value of the guest's state register. The hypervisor may terminate the guest if the update to the state register is unacceptable. Alternatively, the hypervisor may recommend an alternate value to the guest. If the guest agrees, the guest may set the state register to the alternate value recommended by the hypervisor when the guest resumes operation.

Abstract: Embodiments are disclosed that allow data to be sent between a Bluetooth enabled device and a virtual device associated with a corresponding physical device. In particular, embodiments of a virtual mobile device system may include one or more components for processing Bluetooth calls where these Bluetooth components may process received Bluetooth calls in a first manner in a connected state and process Bluetooth calls in a disconnected state in a second manner.

Abstract: Embodiments are disclosed that allow data to be sent between a BLUETOOTH® enabled device and a virtual device associated with a corresponding physical device. In particular, embodiments of a virtual mobile device system may include one or more components for processing BLUETOOTH® calls where these components may process received BLUETOOTH® calls in a first manner in a connected state and process BLUETOOTH® calls in a disconnected state in a second manner.

Abstract: Embodiments are disclosed that allow data to be sent between a Bluetooth enabled device and a virtual device associated with a corresponding physical device. In particular, embodiments of a virtual mobile device system may include one or more components for processing Bluetooth calls where these Bluetooth components may process received Bluetooth calls in a first manner in a connected state and process Bluetooth calls in a disconnected state in a second manner.

Abstract: Embodiments are disclosed that allow encrypted data to be sent between a Bluetooth enabled device and a virtual device associated with a corresponding physical device. In particular, a Bluetooth implementation on the physical device may include one or more raw interfaces to facilitate endpoint to endpoint secure Bluetooth cryptography. Using these raw interfaces, an encrypted Bluetooth channel may be established directly between the virtual device and the Bluetooth enabled device using the radio of the physical device, where data may be encrypted and decrypted at an endpoint of the Bluetooth communication channel (such as at the virtual device or the Bluetooth enabled device) and passed through a Bluetooth implementation on the physical device without any additional encryption or decryption being performed on that data.

Abstract: A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Abstract: Systems, apparatuses, and methods for implementing hypervisor post-write notification of processor state register modifications. A write to a state register of the processor may be detected during guest execution. In response to detecting the write to the state register, the processor may trigger microcode to perform the write and copy the new value of the register to a memory location prior to exiting the guest. The hypervisor may be notified of the update to the state register after it occurs, and the hypervisor may be prevented from modifying the value of the guest's state register. The hypervisor may terminate the guest if the update to the state register is unacceptable. Alternatively, the hypervisor may recommend an alternate value to the guest. If the guest agrees, the guest may set the state register to the alternate value recommended by the hypervisor when the guest resumes operation.

Abstract: A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The system further includes the processor determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Abstract: A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Abstract: A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The system further includes the processor determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Abstract: The present invention provides a method to optimize object code files produced by a compiler for several different types of target processors. The compiler divides the source code to be compiled into several functional modules. Given a specified set of target processors, each functional module is compiled resulting in a target object version for each target processor. Then, for each functional module, a merging process is performed wherein identical target object versions or target object versions with similar contents are merged by deleting the identical or similar versions. After this merging process, a composite object code file is formed containing all of the non-deleted target object versions of the function modules.

Abstract: The present invention provides a method to optimize object code files produced by a compiler for several different types of target processors. The compiler divides the source code to be compiled into several functional modules. Given a specified set of target processors, each functional module is compiled resulting in a target object version for each target processor. Then, for each functional module, a merging process is performed wherein identical target object versions or target object versions with similar contents are merged by deleting the identical or similar versions. After this merging process, a composite object code file is formed containing all of the non-deleted target object versions of the function modules.

Abstract: The present invention provides a method to optimize object code files produced by a compiler for several different types of target processors. The compiler divides the source code to be compiled into several functional modules. Given a specified set of target processors, each functional module is compiled resulting in a target object version for each target processor. Then, for each functional module, a merging process is performed wherein identical target object versions or target object versions with similar contents are merged by deleting the identical or similar versions. After this merging process, a composite object code file is formed containing all of the non-deleted target object versions of the function modules.

Abstract: A computer implemented method, data processing system, and computer program product for dynamically scheduling algorithms in a pipeline which operate on a stream of data. The illustrative embodiments determine a computational cost of each algorithm in a plurality of algorithms in a pipeline. The plurality of algorithms in the pipeline processes an incoming data stream in a first sequential algorithm order. The illustrative embodiments reorder the plurality of algorithms in the pipeline to form a second sequential algorithm order based on the computational cost of each algorithm. The plurality of algorithms may then be executed in the second sequential algorithm order. When the illustrative embodiments assign a spare processing unit to an algorithm at an end of the pipeline, the computational cost of each algorithm in the plurality of algorithms in the pipeline is redetermined.

Abstract: Partition migrations are scheduled between virtual partitions of a virtually partitioned data processing system. The virtually partitioned data processing system is a tickless system in which a periodic timer interrupt is not guaranteed to be sent to the processor at a defined time interval. A request is received for a partition migration. Gaps between scheduled timer interrupts are identified. The partition migration is then scheduled to occur within the largest gap.

Abstract: A computer implemented method for managing an execution mode for a parallel processor is provided. A monitor identifies a first efficiency rate for a first contested resource of the parallel processor operating in a first operating mode. Responsive to identifying the first efficiency rate for the first contested resource, the monitor identifies whether the first efficiency rate for the contested resource of the parallel processor operating in the first operating mode exceeds a threshold. Responsive to identifying that the efficiency rate for the contested resource exceeds the threshold, an operation of the parallel processor is changed to a second operating mode.