Abstract: Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.

Abstract: A method, system, and computer usable program product for energy conservation in multipath data communications are provided in the illustrative embodiments. A current utilization of each of several of I/O devices is determined. A violation determination is made whether an I/O device from the several I/O devices can be powered down without violating a rule. The I/O device is powered down responsive to the violation determination being false. A powering up determination may be made whether an additional I/O device is needed in a multipath I/O configuration. The I/O device may be located, powered up, and made available for multipath I/O configuration. A latency determination may be made whether a latency time of the I/O device can elapse before the time when the additional I/O device is needed. The powering on may occur no later than the latency time before the time the additional I/O device is needed.

Abstract: The illustrative embodiments described herein provide an apparatus and method for managing data in a hybrid drive system. In one embodiment, a process determines whether the detachable memory contains clean data in response to identifying that a cache portion of a detachable memory is unavailable. The clean data does not require a disk to be in a spin state to be removed from the detachable memory. The process removes the clean data from the detachable memory in response to determining that the detachable memory contains the clean data. The process stores the data on the detachable memory.

Abstract: Partition migrations are scheduled between virtual partitions of a virtually partitioned data processing system. The virtually partitioned data processing system is a tickless system in which a periodic timer interrupt is not guaranteed to be sent to the processor at a defined time interval. A request is received for a partition migration. Gaps between scheduled timer interrupts are identified. The partition migration is then scheduled to occur within the largest gap.

Abstract: Methods, systems, and media are disclosed for autonomic system tuning of simultaneous multithreading (“SMT”). In one embodiment, the method for autonomic tuning of at least one SMT setting for an optimized processing, such as via throughput, latency, and power consumption, of a workload on a computer system includes calling, by a kernel, an SMT scheduler having at least one hook into a genetic library. Further, the method includes obtaining, by the SMT scheduler through the at least one hook, genetic data from the genetic library for the optimized processing of the workload. Further still, the method includes tuning, by the SMT scheduler and based on the obtaining, the at least one SMT setting for at least one cpu of the computer system.

Abstract: Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.

Abstract: A method, system, and computer usable program product for energy conservation in multipath data communications are provided in the illustrative embodiments. A current utilization of each of several of I/O devices is determined. A violation determination is made whether an I/O device from the several I/O devices can be powered down without violating a rule. The I/O device is powered down responsive to the violation determination being false. A powering up determination may be made whether an additional I/O device is needed in a multipath I/O configuration. The I/O device may be located, powered up, and made available for multipath I/O configuration. A latency determination may be made whether a latency time of the I/O device can elapse before the time when the additional I/O device is needed. The powering on may occur no later than the latency time before the time the additional I/O device is needed.

Abstract: A computer implemented method, data processing system, and computer program product for dynamically scheduling algorithms in a pipeline which operate on a stream of data. The illustrative embodiments determine a computational cost of each algorithm in a plurality of algorithms in a pipeline. The plurality of algorithms in the pipeline processes an incoming data stream in a first sequential algorithm order. The illustrative embodiments reorder the plurality of algorithms in the pipeline to form a second sequential algorithm order based on the computational cost of each algorithm. The plurality of algorithms may then be executed in the second sequential algorithm order. When the illustrative embodiments assign a spare processing unit to an algorithm at an end of the pipeline, the computational cost of each algorithm in the plurality of algorithms in the pipeline is redetermined.

Abstract: A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.

Abstract: The illustrative embodiments described herein provide an apparatus and method for managing data in a hybrid drive system. In one embodiment, a process determines whether the detachable memory contains clean data in response to identifying that a cache portion of a detachable memory is unavailable. The clean data does not require a disk to be in a spin state to be removed from the detachable memory. The process removes the clean data from the detachable memory in response to determining that the detachable memory contains the clean data. The process stores the data on the detachable memory.

Abstract: Method for balancing a binary search tree. A computer implemented method for balancing a binary search tree includes locating a node in a binary search tree, determining whether a depth of the located node is greater than a threshold, and performing balancing operations. If the depth of the located node is greater than the threshold, the balancing operations may include a modified semi-splay balancing procedure. Regardless of depth, localized balancing operations may be performed while locating a node.

Abstract: Methods, systems, and media are disclosed for autonomic system tuning of simultaneous multithreading (“SMT”). In one embodiment, the method for autonomic tuning of at least one SMT setting for an optimized processing, such as via throughput, latency, and power consumption, of a workload on a computer system includes calling, by a kernel, an SMT scheduler having at least one hook into a genetic library. Further, the method includes obtaining, by the SMT scheduler through the at least one hook, genetic data from the genetic library for the optimized processing of the workload. Further still, the method includes tuning, by the SMT scheduler and based on the obtaining, the at least one SMT setting for at least one cpu of the computer system.

Abstract: A method for managing a mutex in a data processing system is presented. For each mutex, an average acquisition cost is maintained that indicates an average consumption of computational resources that has been incurred by threads attempting to acquire the mutex. If a thread attempts to acquire a locked mutex, then the thread enters a spin state or a sleep state based on restrictive conditions and the average acquisition cost value for the mutex at that time. A thread-specific current acquisition cost value is maintained that represents the consumption of computational resources by the thread after the initial attempt to acquire the mutex and prior to acquiring the mutex. When the thread acquires the mutex, the thread-specific current acquisition cost value is included into the average acquisition cost value.

Abstract: A computer implemented method, data processing system, and a computer program product for improving the scheduling of system processes by the central processing unit. The process retrieves a set of profiling data from an executable object file for the application. The set of profiling data is associated with a given process of the application. The process passes the set of profiling data to a scheduler. The scheduler uses the set of profiling data for scheduling the given process for execution by a processor.

Abstract: A computer implemented method, apparatus, and computer program product for preserving branch history data. The process creates a branch history table in a buffer. The process saves an address for each executed branch instruction that occurs during execution of code in the branch history table to form branch history data. In response to detecting an exception, the process saves the branch history data to an allocated memory space to form a branch history snapshot.

Abstract: A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.

Abstract: A system for managing threads. A kernel tread associated with a user thread is detected as being unneeded by the user tread. The kernel thread is semi-detached in which data for the thread does not change stacks in response to the kernel thread being unneeded.

Abstract: A method, apparatus, and computer instructions for managing threads. A kernel thread associated with a user thread is detected as being unneeded by the user thread. The kernel thread is semi-detached in which data for the thread does not change stacks in response to the kernel thread being unneeded.