Patents by Inventor John A. Coyne

John A. Coyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210088580
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
    Type: Application
    Filed: October 2, 2020
    Publication date: March 25, 2021
    Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
  • Publication number: 20210072304
    Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT.
    Type: Application
    Filed: August 18, 2020
    Publication date: March 11, 2021
    Inventors: Edward John Coyne, John P. Meskell, Colm Patrick Heffernan, Mark Forde, Shane Geary
  • Patent number: 10794950
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 6, 2020
    Assignee: Analog Devices Global
    Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
  • Patent number: 10694352
    Abstract: A system and method is provided for controlling access to software via a physical object. The system may include one or more of a physical object, such as a toy, a computing device, and a server. The toy may include a unique identifier that permits an owner of the toy to download software to the computing device via the server. In some variations, a purchaser of the toy may be permitted to download software to the computing device directly from a storage device associated with the toy.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: June 23, 2020
    Assignee: ACTIVISION PUBLISHING, INC.
    Inventor: John Coyne
  • Publication number: 20190361071
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 28, 2019
    Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
  • Patent number: 10468484
    Abstract: A modified bipolar transistor is provided which can provide improved gain, Early voltage, breakdown voltage and linearity over a finite range of collector voltages. It is known that the gain of a transistor can change with collector voltage. This document teaches a way of reducing this variation by providing structures for the depletion regions with the device to preferentially deplete with. As a result the transistor's response can be made more linear.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: November 5, 2019
    Assignee: Analog Devices Global
    Inventors: Edward John Coyne, William Allan Lane, Seamus P. Whiston
  • Publication number: 20190293692
    Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 26, 2019
    Inventors: David J. Clarke, Stephen Denis Heffernan, Nijun Wei, Alan J. O'Donnell, Patrick Martin McGuinness, Shaun Bradley, Edward John Coyne, David Aherne, David M. Boland
  • Patent number: 10365322
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 30, 2019
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
  • Patent number: 10338132
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global
    Inventors: Edward John Coyne, Alan J. O'Donnell, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Thomas G. O'Dwyer, David Aherne, Michael A. Looby
  • Publication number: 20190131404
    Abstract: A JFET is provided with a very low gate current. In tests the excess gate current above the theoretical minimum current for a similarly sized reverse biased p-n junction was not observed. The JFET includes a lightly doped top gate and doped regions beneath the drain of the JFET.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventor: Edward John Coyne
  • Patent number: 10181719
    Abstract: A protection device is provided that is placed in series connection between an input or signal node and a node to be protected. If the node to be protected is a relatively high impedance node, such as the gate of a MOSFET, then the protection device need not carry much current. This enables it to be built to be very fast. This enables it to respond rapidly to an overvoltage event so as to protect the circuit connected to the node to be protected. The protection device may be used in conjunction with other protection cells that offer greater current carrying capability and controllable trigger voltages, but which are intrinsically slower acting.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 15, 2019
    Assignee: Analog Devices Global
    Inventor: Edward John Coyne
  • Publication number: 20180358248
    Abstract: A temperature shock monitor includes a solvent material and a diffusion material. An energy barrier between the solvent material and the diffusion material is selected to be lower than is would conventionally be used in semiconductor devices such that the diffusion material diffuses into the solvent material when exposed to a temperature above a designated temperature threshold. At a later time, electrical parameters of the temperature shock monitor that change based on the amount of diffusion of the diffusion material into the solvent material allows one to determine whether the temperature shock monitor was exposed to a temperature above the temperature threshold.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 13, 2018
    Inventor: Edward John Coyne
  • Patent number: 10148263
    Abstract: A combined isolator and power switch is disclosed. Such devices are useful in isolating low voltage components such as control compilers from motors or generators working at high voltages. The combined isolator and power switch includes circuits to transfer internal power from its low voltage side to the switch driver circuits on the high voltage side. The combined isolator and switch is compact and easy to use.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: December 4, 2018
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Edward John Coyne, Patrick Martin McGuinness, William Allan Lane, Laurence O'Sullivan
  • Patent number: 10134028
    Abstract: The present invention relates to methods and systems involving a gift card comprising a principal value and auxiliary value. The principal value may represent a monetary or pre-sale value, while the auxiliary value may represent a virtual good.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 20, 2018
    Assignee: Activision Publishing, Inc.
    Inventor: John Coyne
  • Patent number: 10043792
    Abstract: An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 7, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Edward John Coyne, Patrick Martin McGuinness, Paul Malachy Daly, Bernard Patrick Stenson, David J. Clarke, Andrew David Bain, William Allan Lane
  • Patent number: 10010795
    Abstract: The present invention generally relates to methods and systems involving an enhanced social expression card that comprises machine-readable storage for data relating to one or more virtual goods. The one or more virtual goods may be, for example, redeemable in a virtual environment such as a videogame or an online virtual world.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: July 3, 2018
    Assignee: Activision Publishing, Inc.
    Inventor: John Coyne
  • Patent number: 9935628
    Abstract: A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: April 3, 2018
    Assignee: Analog Devices Global
    Inventor: Edward John Coyne
  • Publication number: 20170299650
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 19, 2017
    Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
  • Publication number: 20170299649
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.
    Type: Application
    Filed: October 12, 2016
    Publication date: October 19, 2017
    Inventors: Edward John Coyne, Alan J. O'Donnell, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Thomas G. O'Dwyer, David Aherne, Michael A. Looby
  • Publication number: 20170279444
    Abstract: A combined isolator and power switch is disclosed. Such devices are useful in isolating low voltage components such as control compilers from motors or generators working at high voltages. The combined isolator and power switch includes circuits to transfer internal power from its low voltage side to the switch driver circuits on the high voltage side. The combined isolator and switch is compact and easy to use.
    Type: Application
    Filed: July 21, 2016
    Publication date: September 28, 2017
    Inventors: Edward John Coyne, Patrick Martin McGuinness, William Allan Lane, Lawrence O'Sullivan