Abstract: The present disclosure relates to a method of generating a high differential read current through a non-volatile memory, including receiving a voltage read input from a word line voltage generator, outputting a first current to a bit line true (BLT), outputting a second current to a bit line complement (BLC), and generating the high differential read current through a difference between the first current and the second current.

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.

Abstract: A power distribution system including a high-voltage direct current unit (HVDCU) configured to receive an amount of high-frequency alternating current (AC) input power from a power source and convert the input power into DC power, a negative voltage distribution rail and a positive voltage distribution rail that are together configured to supply the high-voltage DC power to at least one control unit (CU) electrically disposed between the negative voltage distribution rail and the positive voltage distribution rail and the CU being configured to convert the DC power into output power compatible with at least one load and supply the output power to the loads associated with it.

Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

Abstract: Disclosed is an op-amp circuit with current-controlled hysteresis that is insensitive to PVT variations. In the circuit, a digital output signal is output from an output buffer based on the output voltage at an output node of an op-amp. A current source is connected to the input side of the op-amp or one of multiple current sources is selectively connected to the input side and enabled when the digital output signal has a high value to provide falling edge hysteresis. Alternatively, a current source is connected to the reference side of the op-amp or one of multiple current sources is selectively connected to the reference side and enabled when the digital output signal is low to provide rising edge hysteresis. Alternatively, current sources are connected to both the input and reference sides and selectively controlled to provide either falling or rising edge hysteresis.

Abstract: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Abstract: Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.

Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Abstract: An approach of operating a voltage pump system for a semiconductor chip. The approach includes one or more voltage pumps receiving a pair of clock signal inputs. The approach includes activating a first group of voltage pumps with a high clock signal level and activating a second group of voltage pumps activate with a low clock signal level. Furthermore, the approach includes deriving the pair of clock signal inputs from an oscillator and a hold circuit and configuring a current clock signal output level to latch upon receipt of a hold signal.

Abstract: Electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an integrated circuit from a transient electrostatic discharge event. The electrostatic discharge protection circuit includes a power clamp device, a first timing circuit with a first resistor and a first capacitor that is coupled with the first resistor at a first node, and a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node. The electrostatic discharge protection circuit further includes a logic gate with a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device. The logic gate responds to voltages at the first and second nodes to control the impedance state of the power clamp device.

Abstract: A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

Abstract: A nano-magnetic element array having a conductive line adjacent to a group of nano-magnetic elements and a multi-level current driver connected to an input node on the conductive line. The current driver is controlled by a pair of voltage clock signals and a voltage reference so as to selectively change the current amount at the input node between a first level that erases the state of the elements, a second level that switches the state of the elements and a third level that maintains the state of the elements. The current driver is further configured so that the transition from the second to the third level is gradual. Optionally, a bias generator can selectively adjust the voltage reference and thereby, the current amount at the input node. Also, optionally, the same voltage clock signal and voltage reference lines can be used to control multiple multi-level current drivers within the array.

Abstract: Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.

Abstract: A semiconductor structure including a device configured to receive an input data-word. The device including a logic structure configured to generate an encrypted data-word by encrypting the input data-word through an encrypting operation. The device further including an eFuse storage device configured to store the encrypted data-word as eFuse data by blowing fuses in accordance with the encrypted data-word.

Abstract: Methods, systems, and structures for generating a target reference voltage are provided. A circuit includes a voltage adjuster, a switch, and a current source. The switch selectively connects the current source to circuit paths in the voltage adjuster. A first of the circuit paths incrementally decreases the target reference voltage with respect to the input voltage. A second of the circuit paths incrementally increases the target voltage with respect to the input voltage.