Patents by Inventor John A. SCHUMANN
John A. SCHUMANN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10896273Abstract: A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.Type: GrantFiled: October 12, 2018Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Schumann, Debapriya Chatterjee, Bryant Cockcroft, Kevin Barnett, Piriya K. Hall, Paul Umbarger, Karen Yokum
-
Publication number: 20200371951Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
-
Publication number: 20200364313Abstract: Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.Type: ApplicationFiled: May 15, 2019Publication date: November 19, 2020Inventors: Paul Umbarger, Debapriya Chatterjee, Karen Yokum, John A. Schumann, Bryant Cockcroft, Kevin Barnett
-
Patent number: 10754791Abstract: Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.Type: GrantFiled: January 2, 2019Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vivek Britto, Bryant Cockcroft, John Schumann, Tharunachalam Pindicura, Shricharan Srivatsan, Yan Xia, Aishwarya Dhandapani
-
Publication number: 20200225952Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
-
Patent number: 10705843Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: GrantFiled: December 21, 2017Date of Patent: July 7, 2020Assignee: International Business Machines CorporationInventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
-
Publication number: 20200210346Abstract: Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.Type: ApplicationFiled: January 2, 2019Publication date: July 2, 2020Inventors: VIVEK BRITTO, BRYANT COCKCROFT, John Schumann, Tharunachalam Pindicura, SHRICHARAN SRIVATSAN, YAN XIA, AISHWARYA DHANDAPANI
-
Publication number: 20200201767Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes issuing from one of a plurality of processors an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system; broadcasting the address translation invalidation instruction to one or more storage locations of one or more of the other processors; invalidating an address translation entry located in a storage location of the one or more storage locations; and returning information on the invalidated address translation entry to the issuing processor.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: John A. Schumann, Debapriya Chatterjee, Bryant Cockcroft, Lawrence Leitner, Karen Yokum
-
Publication number: 20200201739Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Shricharan Srivatsan, Vivek Britto, Aishwarya Dhandapani, Tharunachalam Pindicura, John A. Schumann, Brian W. Thompto
-
Publication number: 20200150961Abstract: A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Shakti Kapoor, Karen E. Yokum, John A. Schumann
-
Publication number: 20200117766Abstract: A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.Type: ApplicationFiled: October 12, 2018Publication date: April 16, 2020Inventors: JOHN A. SCHUMANN, DEBAPRIYA CHATTERJEE, BRYANT COCKCROFT, KEVIN BARNETT, PIRIYA K. HALL, PAUL UMBARGER, KAREN YOKUM
-
Patent number: 10579376Abstract: A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.Type: GrantFiled: July 15, 2016Date of Patent: March 3, 2020Assignee: International Business Machines CorporationInventors: Shakti Kapoor, John A. Schumann, Karen E. Yokum
-
Patent number: 10539614Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.Type: GrantFiled: November 7, 2017Date of Patent: January 21, 2020Assignee: International Business Machines CorporationInventors: Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann, Karen E. Yokum
-
Publication number: 20190196816Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
-
Patent number: 10228422Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit. Execution of one or more scripts select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.Type: GrantFiled: May 15, 2017Date of Patent: March 12, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Debapriya Chatterjee, Shakti Kapoor, John A. Schumann
-
Patent number: 10007568Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.Type: GrantFiled: April 12, 2016Date of Patent: June 26, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manoj Dusanapudi, Shakti Kapoor, Paul F. Lecocq, John A. Schumann
-
Publication number: 20180120379Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit. Execution of one or more scripts select the initialization sequence from a plurality of test cases, set the breakpoint, modify a state of the circuit design as the next action to perform, and capture a plurality of test results based on execution of the initialization sequence through the interface unit.Type: ApplicationFiled: May 15, 2017Publication date: May 3, 2018Inventors: Debapriya Chatterjee, Shakti Kapoor, John A. Schumann
-
Patent number: 9939487Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.Type: GrantFiled: December 18, 2015Date of Patent: April 10, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rahul Batra, Debapriya Chatterjee, John C. Goss, Christopher R. Jones, Christopher M. Riedl, John A. Schumann, Karen E. Yokum
-
Patent number: 9921897Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.Type: GrantFiled: January 6, 2016Date of Patent: March 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manoj Dusanapudi, Shakti Kapoor, Paul F. Lecocq, John A. Schumann
-
Publication number: 20180059182Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.Type: ApplicationFiled: November 7, 2017Publication date: March 1, 2018Inventors: Rahul BATRA, Debapriya CHATTERJEE, John C. GOSS, Christopher R. JONES, Christopher M. RIEDL, John A. SCHUMANN, Karen E. YOKUM