Abstract: A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.

Abstract: An aspect includes driving a plurality of commands to an interface unit of a circuit design in a hardware-accelerated simulator to dynamically initialize the circuit design to run one or more test cases based on an initialization sequence with breakpoint support. A state of the circuit design is examined through the interface unit based on triggering of a breakpoint on the hardware-accelerated simulator. A next action to perform in the initialization sequence is determined based on the state of the circuit design as determined through the interface unit.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.

Abstract: A method includes executing a first post-silicon testing program by a reference model. During the execution of the first post-silicon testing program, one or more test-cases are generated. The first post-silicon testing program is executed in an offline generation mode. During execution of the first post-silicon testing program each test case is generated in a different memory location. After the execution, generating a second post-silicon testing program that is configured to execute the one or more test-cases. The method further includes executing the second post-silicon testing program on an acceleration platform.

Abstract: A method, apparatus and product for hardware verification using acceleration platform. The method comprising executing a first post-silicon testing program by a reference model, wherein during said executing the first post-silicon testing program one or more test-cases are generated; generating a second post-silicon testing program that is configured to execute the one or more test-cases; and executing the second post-silicon testing program on an acceleration platform.