Patents by Inventor John B. Dillon
John B. Dillon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6589059Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.Type: GrantFiled: September 20, 2001Date of Patent: July 8, 2003Assignee: Rambus, Inc.Inventors: Donald V. Perino, Wayne S. Richardson, John B. Dillon
-
Patent number: 6556052Abstract: A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.Type: GrantFiled: September 12, 2001Date of Patent: April 29, 2003Inventors: Billy Wayne Garrett, Jr., John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
-
Patent number: 6504875Abstract: A system for transmitting information from a source to a destination using multilevel signaling. Multiple conductors are coupled between the transmission source and the transmission destination. Multiple drivers are coupled to the conductors at the transmission source. Each driver is coupled to a pair of conductors. Multiple comparators are coupled to the conductors at the transmission destination. Each comparator is coupled to a pair of conductors. The information is encoded into a sequence of symbols in which each symbol represents a unique permutation of signal levels on the conductors. Each signal level is used at least once for each symbol. All signal levels associated with a particular symbol are transmitted over the conductors simultaneously.Type: GrantFiled: October 31, 2001Date of Patent: January 7, 2003Assignee: Rambus Inc.Inventors: Donald V. Perino, John B. Dillon
-
Publication number: 20020196059Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: ApplicationFiled: August 29, 2002Publication date: December 26, 2002Inventors: Billy Wayne Garrett, John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, Nancy David Dillon
-
Publication number: 20020186777Abstract: A system for transmitting information from a source to a destination using multilevel signaling. Multiple conductors are coupled between the transmission source and the transmission destination. Multiple drivers are coupled to the conductors at the transmission source. Each driver is coupled to a pair of conductors. Multiple comparators are coupled to the conductors at the transmission destination. Each comparator is coupled to a pair of conductors. The information is encoded into a sequence of symbols in which each symbol represents a unique permutation of signal levels on the conductors. Each signal level is used at least once for each symbol. All signal levels associated with a particular symbol are transmitted over the conductors simultaneously.Type: ApplicationFiled: October 31, 2001Publication date: December 12, 2002Inventors: Donald V. Perino, John B. Dillon
-
Patent number: 6462591Abstract: A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.Type: GrantFiled: June 14, 2001Date of Patent: October 8, 2002Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., John B. Dillon, by Nancy David Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
-
Patent number: 6447321Abstract: A method and apparatus for an integrated circuit package is provided. The integrated circuit package is designed for coupling an integrated circuit to a printed circuit board. The integrated circuit package includes a base having a bottom and a side. A flex circuit having traces therein is coupled to the base. The traces in the flex circuit are designed to couple to the leads of the integrated circuit. The traces further are designed to couple to traces on the printed circuit board.Type: GrantFiled: November 18, 1999Date of Patent: September 10, 2002Assignee: Rambus, Inc.Inventors: Donald V. Perino, John B. Dillon
-
Publication number: 20020095560Abstract: A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.Type: ApplicationFiled: January 18, 2002Publication date: July 18, 2002Inventors: Richard M. Barth, Ely K. Tsern, Mark A. Horowitz, Donald C. Stark, Craig E. Hampel, Frederick A. Ware, John B. Dillon, Nancy David Dillon
-
Publication number: 20020070771Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: ApplicationFiled: September 12, 2001Publication date: June 13, 2002Inventors: Billy Wayne Garrett, John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, Nancy David Dillon
-
Publication number: 20020055285Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.Type: ApplicationFiled: September 20, 2001Publication date: May 9, 2002Applicant: Rambus, Inc.Inventors: Donald V. Perino, Wayne S. Richardson, John B. Dillon
-
Patent number: 6359931Abstract: A system for transmitting information from a source to a destination using multilevel signaling. Multiple conductors are coupled between the transmission source and the transmission destination. Multiple drivers are coupled to the conductors at the transmission source. Each driver is coupled to a pair of conductors. Multiple comparators are coupled to the conductors at the transmission destination. Each comparator is coupled to a pair of conductors. The information is encoded into a sequence of symbols in which each symbol represents a unique permutation of signal levels on the conductors. Each signal level is used at least once for each symbol. All signal levels associated with a particular symbol are transmitted over the conductors simultaneously.Type: GrantFiled: October 15, 1999Date of Patent: March 19, 2002Assignee: Rambus Inc.Inventors: Donald V. Perino, John B. Dillon
-
Publication number: 20020031923Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.Type: ApplicationFiled: September 20, 2001Publication date: March 14, 2002Inventors: Donald V. Perino, Wayne S. Richardson, John B. Dillon
-
Patent number: 6356975Abstract: A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.Type: GrantFiled: October 9, 1998Date of Patent: March 12, 2002Assignee: Rambus IncorporatedInventors: Richard M. Barth, Ely K. Tsern, Mark A. Horowitz, Donald C. Stark, Craig E. Hampel, Frederick A. Ware, John B. Dillon, by Nancy David Dillon
-
Patent number: 6352435Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.Type: GrantFiled: December 20, 1999Date of Patent: March 5, 2002Assignee: Rambus, Inc.Inventors: Donald V. Perino, Wayne S. Richardson, John B. Dillon
-
Publication number: 20020017929Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: ApplicationFiled: June 14, 2001Publication date: February 14, 2002Inventors: Billy Wayne Garrett, John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin, Nancy David Dillon
-
Publication number: 20020016091Abstract: A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.Type: ApplicationFiled: September 20, 2001Publication date: February 7, 2002Applicant: Rambus, Inc.Inventors: Donald V. Perino, Wayne S. Richardson, John B. Dillon
-
Patent number: 6294934Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: April 26, 2000Date of Patent: September 25, 2001Assignee: Rambus Inc.Inventors: Billy Wayne Garrett, Jr., John B. Dillon, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin
-
Patent number: 6234820Abstract: A method and apparatus for joining printed circuit boards is provided. A socket is attached to a mother board. A connector is attached to a daughter board. The traces on the daughter board are connected to signal leads, which are wrapped around an elastomer. The socket and the connector are engaged, such that the mother board is coupled to a daughter board, and the traces on the mother board are coupled to the signal leads of the daughter board.Type: GrantFiled: July 21, 1997Date of Patent: May 22, 2001Assignee: Rambus Inc.Inventors: Donald V. Perino, John B. Dillon
-
Patent number: 6205191Abstract: A synchronization circuit for gradually shifting the phase domain of a control signal to permit synchronization of a signal with a clock signal in a different phase domain in a system with a single frequency, but arbitrary phase relationship. The present invention allows a control signal in the phase domain of an internal clock to be synchronized with an external clock, when the phase domain of the external clock differs substantially from that of the internal clock. In synchronizing the control signal to the external clock, the present invention avoids the generation of runt pulses while providing a control signal synchronized to the external clock in the least amount of time feasible (i.e., with the lowest latency time). Because the present invention has no failure modes due to timing relationships, MTBF is infinite for failures caused by such relationships and therefore need not be a concern. This also implies that no risk is posed to the proper operation of the circuits driven thereby.Type: GrantFiled: July 21, 1997Date of Patent: March 20, 2001Assignee: Rambus Inc.Inventors: Clemenz Portmann, John B. Dillon
-
Patent number: 6094075Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).Type: GrantFiled: August 27, 1998Date of Patent: July 25, 2000Assignee: Rambus IncorporatedInventors: Billy Wayne Garrett, Jr., John B. Dillon, deceased, Michael Tak-Kei Ching, William F. Stonecypher, Andy Peng-Pui Chan, Matthew M. Griffin